OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 60

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
6.4 Register description
Table 60.
UM10441
User manual
Name
-
-
PIO0_19
PIO0_20
PIO0_21
PIO0_22
PIO0_23
PIO0_24
SWDIO_PIO0_25
SWCLK_PIO0_26
PIO0_27
PIO2_12
PIO2_13
PIO2_14
PIO2_15
PIO0_28
PIO0_29
PIO0_0
PIO0_1
PIO0_2
-
PIO0_3
PIO0_4
PIO0_5
Register overview: I/O configuration block (base address 0x4004 4000)
If the sensitivity to noise spikes must be minimized, select a slower PCLK and lower
sample mode.
Table 60
register which allows to program its function and electrical characteristics. The register
name is derived from the pin’s default function after reset. Note that some pins reset to
functions other than GPIO. The corresponding registers are indicated by a prefix reflecting
the pin’s function after reset: Either a serial wire debug function (SWDIO or SWCLK) or a
reserved function (R).
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
shows the IOCONFIG registers. Each multiplexed pin is associated with one
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
All information provided in this document is subject to legal disclaimers.
Description
Reserved.
Reserved.
Configures pin
PIO0_19/ACMP0_I0/CT32B0_1.
Configures pin
PIO0_20/ACMP0_I1/CT32B0_2.
Configures pin
PIO0_21/ACMP0_I2/CT32B0_3.
Configures pin PIO0_22/ACMP0_I3.
Configures pin
PIO0_23/ACMP1_I0/CT32B1_0.
Configures pin
PIO0_24/ACMP1_I1/CT32B1_1.
Configures pin SWDIO/ACMP1_I2/
CT32B1_2/PIO0_25.
Configures pin SWCLK/PIO0_26/ACMP1_I3/
CT32B1_3/PIO0_26
Configures pin PIO0_27/ACMP0_O.
Configures pin PIO2_12/RXD1.
Configures pin PIO2_13/TXD1.
Configures pin PIO2_14.
Configures pin PIO2_15.
Configures pin
PIO0_28/ACMP1_O/CT16B0_0.
Configures pin PIO0_29/ROSC/CT16B0_1.
Configures pin PIO0_0/RTS0.
Configures pin PIO0_1CT32B0_0/RXD0.
Configures pin PIO0_2/TXD0/CT32B0_1.
Reserved
Configures pin PIO0_3/DTR0/CT32B0_2.
Configures pin PIO0_4/DSR0/CT32B0_3.
Configures pin PIO0_5.
Rev. 1.1 — 10 March 2011
Chapter 6: LPC122x I/O configuration (IOCONFIG)
Reset value
-
-
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
-
0x0000 0090
0x0000 0090
0x0000 0090
UM10441
© NXP B.V. 2011. All rights reserved.
Reference
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Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
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Table 81
Table 82
Table 83
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