OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 284

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 269: Watchdog Timer Clock Source Selection register (CLKSEL - address 0x4000 4010) bit description
UM10441
User manual
Bit
1:0
30:2
31
Symbol
WDSEL
-
WDLOCK
17.7.4 Watchdog Timer Value register
17.7.5 Watchdog Timer Clock Source Selection Register
Value
0x0
0x1
0x2
0x3
-
0
1
The WDTV register is used to read the current value of Watchdog timer counter.
When reading the value of the 24-bit counter, the lock and synchronization procedure
takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the
actual value of the timer when it's being read by the CPU.
Table 268. Watchdog Timer Value register (TV - 0x4000 400C) bit description
This register allows selecting the clock source for the Watchdog timer. The clock source
selection bits can be locked by software using bit 31 of this register, so that they cannot be
modified. In addition, changes to the clock source are ignored if not both the watchdog
oscillator and the IRC are powered in the PDRUNCFG register. This prevents the user
from switching to a non-existing clock source.
If the WDT is running in Deep-sleep mode, the watchdog oscillator must be selected as
clock source.
On reset, the clock source selection bits are always unlocked.
Bit
23:0
31:24
Description
These bits select the clock source for the Watchdog timer as described below.
Warning: Improper setting of this value may result in incorrect operation of the
Watchdog timer, which could adversely affect system operation. If the WDLOCK
bit in this register is set, the WDSEL bits cannot be modified.
Remark: Writes to the WDSEL bits are ignored if the corresponding clock source
is powered down in the PDRUNCFG register
Selects the Internal RC oscillator as the Watchdog clock source (default). In
active mode only.
Selects the watchdog oscillator as the Watchdog clock source. Must be selected
if the WDT is running in Deep-sleep mode.
Reserved. Do not use.
Reserved. Do not use.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Lock Watchdog clock source.
This bit is set to 0 on any reset. It cannot be cleared by software.
Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this
register cannot be modified.
Symbol
Count
-
All information provided in this document is subject to legal disclaimers.
Description
Counter timer value.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 1.1 — 10 March 2011
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
(Table
50).
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0x00 00FF
NA
284 of 442
Reset
value
00
NA
0