OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 162

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
10.5.1 UART Receiver Buffer Register (when DLAB = 0, Read Only)
10.5.2 UART Transmitter Holding Register (when DLAB = 0, Write Only)
10.5.3 UART Divisor Latch LSB and MSB Registers (when DLAB = 1)
The RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the
oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the RBR.
The RBR is always Read Only.
Since PE, FE and BI bits (see
RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach
for fetching the valid pair of received byte and its status bits is first to read the content of
the LSR register, and then to read a byte from the RBR.
Table 162. UART Receiver Buffer Register (RBR - address 0x4000 C000 when DLAB = 0,
The THR is the top byte of the UART TX FIFO. The top byte is the newest character in the
TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the THR.
The THR is always Write Only.
Table 163. UART Transmitter Holding Register (THR - address 0x4000 C000 when DLAB = 0,
The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value
used, along with the Fractional Divider, to divide the UART_PCLK clock in order to
produce the baud rate clock, which must be 16x the desired baud rate. The DLL and DLM
registers together form a 16-bit divisor where DLL contains the lower 8 bits of the divisor
and DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001
value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in LCR must
be one in order to access the UART Divisor Latches. Details on how to select the right
value for DLL and DLM can be found in
Bit
7:0
31:8 -
Bit
7:0
31:8 -
RBR
THR
Symbol
Symbol
Read Only) bit description
Write Only) bit description
All information provided in this document is subject to legal disclaimers.
Description
The UART Receiver Buffer Register contains the oldest received
byte in the UART RX FIFO.
Reserved
Description
Writing to the UART Transmit Holding Register causes the data
to be stored in the UART transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
Reserved
Rev. 1.1 — 10 March 2011
Table
171) correspond to the byte sitting on the top of the
Section
10.5.12.
Chapter 10: LPC122x UART1
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
undefined
-
Reset value
NA
-
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