OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 363

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.3.1.4 Exceptions and interrupts
25.3.1.5 Data types
25.3.1.6 The Cortex Microcontroller Software Interface Standard
Table 359. CONTROL register bit assignments
Handler mode always uses the MSP, so the processor ignores explicit writes to the active
stack pointer bit of the CONTROL register when in Handler mode. The exception entry
and return mechanisms update the CONTROL register.
In an OS environment, it is recommended that threads running in Thread mode use the
process stack and the kernel and exception handlers use the main stack.
By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode
to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see
Section
Remark: When changing the stack pointer, software must use an ISB instruction
immediately after the MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer. See
The Cortex-M0 processor supports interrupts and system exceptions. The processor and
the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An
interrupt or exception changes the normal flow of software control. The processor uses
handler mode to handle all exceptions except for reset. See
Section 25–25.3.3.6.2
The NVIC registers control interrupt handling. See
information.
The processor:
ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for
programming Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device
driver library.
Bits
[31:2]
[1]
[0]
•
•
supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
manages all data memory accesses as little-endian. Instruction memory and Private
Peripheral Bus (PPB) accesses are always little-endian. See
more information.
25–25.4.7.6.
All information provided in this document is subject to legal disclaimers.
Name
-
Active stack
pointer
-
Rev. 1.1 — 10 March 2011
for more information.
Section
Function
Reserved
Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
In Handler mode this bit reads as zero and ignores writes.
Reserved.
Chapter 25: LPC122x Appendix ARM Cortex-M0
25–25.4.7.5.
Section 25–25.5.2
Section 25–25.3.3.6.1
Section 25–25.3.2.1
for more
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