OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 337

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.6.18 Channel DMA interrupt status register
21.6.19 DMA error interrupt enable register
Table 337. Bus error clear register (ERR_CLR, address 0x4004 C04C) bit description
This register is a read/write register and shows the DMA done interrupt status for each
DMA channel c (c = 0 to 20). Writing a one clears the status bit. Writing to a bit where a
DMA channel is not implemented has no effect.
Table 338. Channel DMA interrupt status register (CHNL_IRQ_STATUS, address 0x4004
This register is a read/write register and enables the DMA error interrupt. Writing to a bit
where a DMA channel is not implemented has no effect.
Table 339. DMA error interrupt enable register (IRQ_ERR_ENABLE, address 0x4004 C084)
Bit
0
31:1
Bit
20:0
31:21 -
Bit
0
31:1 -
Symbol
IRQ_ERR_ENABLE Enables the DMA error (dma_error) signal to create an
Symbol
CHNL_IRQ_
STAT
Symbol
ERR_CLR
-
C080) bit description
bit description
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Description
Read as:
0 = dma_err is LOW.
1 = dma_err is HIGH.
Write as:
0 = No effect, status of dma_err is unchanged.
1 = Sets dma_err LOW.
Returns the status of dma_error or sets the signal LOW.
Reserved. Write as 0.
Rev. 1.1 — 10 March 2011
Description
Returns the status of the DMA done interrupt for each channel.
Read as:
Bit [c] = 0: DMA done interrupt not asserted.
Bit [c] = 1: DMA transfer complete for Channel c.
Write as:
Bit [c] = 0: No effect.
Bit [c] = 1: Clears the DMA done status for Channel c.
Reserved.
Chapter 21: LPC122x General purpose micro DMA controller
Description
interrupt.
Write as:
Bit 0 = 0: DMA error interrupt disabled.
Bit 0 = 1: DMA error interrupt enabled.
Reserved.
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
-
0x0
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Reset
value
0x0
-
Reset
value
0x0
-