OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 227

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
12.6.3 SSP Data Register
12.6.4 SSP Status Register
12.6.5 SSP Clock Prescale Register
Software can write data to be transmitted to this register, and read data that has been
received.
Table 208. SSP Data Register (DR - address 0x4004 0008) bit description
This read-only register reflects the current status of the SSP controller.
Table 209. SSP Status Register (SR - address 0x4004 000C bit description
This register controls the factor by which the Prescaler divides the SSP peripheral clock
SSP_PCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in CR0,
to determine the bit clock.
4
31:5
Bit
15:0
31:16 -
Bit
0
1
2
3
Symbol
DATA
Symbol
TFE
TNF
RNE
RFF
BSY
-
All information provided in this document is subject to legal disclaimers.
Description
Write: software can write data to be sent in a future frame to this
register whenever the TNF bit in the Status register is 1,
indicating that the Tx FIFO is not full. If the Tx FIFO was
previously empty and the SSP controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the
data written to this register will be sent as soon as all previous
data has been sent (and received). If the data length is less than
16 bit, software must right-justify the data written to this register.
Read: software can read data from this register whenever the
RNE bit in the Status register is 1, indicating that the Rx FIFO is
not empty. When software reads this register, the SSP controller
returns data from the least recent frame in the Rx FIFO. If the
data length is less than 16 bit, the data is right-justified in this
field with higher order bits filled with 0s.
Reserved
Description
Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
empty, 0 if not.
Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1
Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is
empty, 1 if not.
Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if
not.
Busy. This bit is 0 if the SSP controller is idle, or 1 if it is
currently sending/receiving a frame and/or the Tx FIFO is not
empty.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 1.1 — 10 March 2011
Chapter 12: LPC122x SSP controller
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0x0000
-
Reset value
1
0
0
0
NA
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