OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 185

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.7.2 I
11.7.3 I
11.7.4 I
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
Each I
Status register is Read-Only.
Table 183. I
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
Table 184. I
This register is readable and writable and are only used when an I
slave mode. In master mode, this register has no effect. The LSB of I2ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
Any of these registers which contain the bit 00x will be disabled and will not match any
address on the bus. This register will be cleared to this disabled state on reset.
Bit Symbol
2:0 -
7:3 Status
31:
8
Bit Symbol
7:0 Data
31:
8
2
2
2
1. A data byte has been received while the I
2. A data byte has been received while the I
C Status register (STAT - 0x4000 0004)
C Data register (DAT - 0x4000 0008)
C Slave Address register 0 (ADR0- 0x4000 000C)
-
-
2
C Status register reflects the condition of the corresponding I
2
2
C Status register (STAT - 0x4000 0004) bit description
C Data register (DAT - 0x4000 0008) bit description
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
Reserved
All information provided in this document is subject to legal disclaimers.
Description
This register holds data values that have been received or are to
be transmitted.
Reserved
Rev. 1.1 — 10 March 2011
2
C states. When any of these states entered, the SI bit will
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode.
Chapter 11: LPC122x I2C-bus controller
Table 199
2
C interface. 0x1F
2
C interface is set to
2
C interface. The I
UM10441
© NXP B.V. 2011. All rights reserved.
to
-
Table
Reset value
0
0
Reset value
-
185 of 442
202.
2
C