OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 258

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 236: Interrupt Register (IR, address 0x4001 8000 (CT32B0) and IR, address 0x4001 C000) bit description
UM10441
User manual
Bit
0
1
2
3
4
5
6
7
31:8
Symbol
MR0INT
MR1INT
MR2INT
MR3INT
CR0INT
CR1INT
CR2INT
CR3INT
-
14.7.2 Timer Control Register
14.7.3 Timer Counter registers
14.7.4 Prescale Register
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 237: Timer Control Register (TCR, address 0x4001 8004 (CT32B0) and 0x4001 C004
The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
Table 238: Timer counter registers (TC, address 0x4001 8008 (CT32B0) and 0x4001 C008
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
Bit
0
1
31:2
Bit
31:0
Symbol Value
CEN
CRST
-
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Interrupt flag for capture channel 1 event.
Interrupt flag for capture channel 2 event.
Interrupt flag for capture channel 3 event.
Reserved
Symbol
TC
(CT32B1)) bit description
(CT32B1)) bit description
All information provided in this document is subject to legal disclaimers.
0
1
0
1
Rev. 1.1 — 10 March 2011
Description
Timer counter value.
Description
Counter enable.
The counters are disabled.
The Timer Counter and Prescale Counter are enabled
for counting.
Counter reset.
Do nothing.
The Timer Counter and the Prescale Counter are
synchronously reset on the next positive edge of PCLK.
The counters remain reset until TCR[1] is returned to
zero.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0
0
0
0
0
0
-
Reset
value
0
0
NA
258 of 442
Reset
value
0