OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 264

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 245: External Match Register (EMR, address 0x4001 803C (CT32B0) and 0x4001 C03C (CT32B1)) bit
Table 246. External match control
UM10441
User manual
Bit
31:12 -
EMR[11:10], EMR[9:8],
EMR[7:6], or EMR[5:4]
Symbol
14.7.10.1 DMA operation
description
14.7.11 Count Control Register
00
01
10
11
Value Description
0x2
0x3
DMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits of
each timer. In order to have an effect, the GPDMA must be configured and the relevant
timer DMA request selected as a DMA source. When a timer is initially set up to generate
a DMA request, the request may already be asserted before a match condition occurs. An
initial DMA request may be avoided by having software write a one to clear the timer
interrupt flag. A DMA request will be automatically cleared via hardware by the DMA
controller after servicing.
request is generated even if the corresponding MR register is set to 0 because a
match-on-zero condition exists. To disable any DMA requests, set the EMR bits for
channels 0 and 1 to 00.
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOWLOW levels on the same CAP input
in this case can not be shorter than 1/PCLK.
If the EMR bits are set to 10 or 11 for channels 0 or 1 (rising edge or toggle), a DMA
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
NA