OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 193

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.8.3 Slave Receiver mode
11.8.4 Slave Transmitter mode
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, write any of the Slave Address registers (ADR0-3) and Slave
Mask registers (MASK0-3) and write the I
Table
Table 195. CONSET used to configure Slave mode
I2EN must be set to 1 to enable the I
any of its own slave addresses or the General Call address. The STA, STO and SI bits are
set to 0.
After ADR and CONSET are initialized, the I
any of its own slave addresses or General Call address followed by the data direction bit.
If the direction bit is 0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it
enters slave transmitter mode. After the address and direction bit have been received, the
SI bit is set and a valid status code can be read from the Status register (STAT). Refer to
Table 201
The first byte is received and handled as in the slave receiver mode. However, in this
mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via
SDA while the serial clock is input through SCL. START and STOP conditions are
recognized as the beginning and end of a serial transfer. In a given application, I
operate as a master and as a slave. In the slave mode, the I
its own slave addresses and the General Call address. If one of these addresses is
detected, an interrupt is requested. When the microcontrollers wishes to become the bus
master, the hardware waits until the bus is free before the master mode is entered so that
a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the
I
addresses in the same serial transfer.
2
Bit
Symbol
Value
Fig 17. Format of Slave Receiver mode
C interface switches to the slave mode immediately and can detect any of its own slave
S
from Master to Slave
from Slave to Master
195.
SLAVE ADDRESS
for the status codes and actions.
7
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All information provided in this document is subject to legal disclaimers.
6
I2EN
1
Rev. 1.1 — 10 March 2011
RW=0
5
STA
0
2
A
C function. AA bit must be set to 1 to acknowledge
4
STO
0
2
C Control Set register (CONSET) as shown in
2
DATA
C interface waits until it is addressed by its
Chapter 11: LPC122x I2C-bus controller
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Sr = Repeated START condition
3
SI
0
n bytes data received
A
2
2
AA
1
C hardware looks for any of
DATA
UM10441
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1
© NXP B.V. 2011. All rights reserved.
A/A
2
0
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C may
P/Sr