OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 279

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
17.5 Clocking and power control
UM10441
User manual
When a watchdog window is programmed, an early watchdog feed is also treated as a
watchdog event. This allows preventing situations where a system failure may still feed
the watchdog. For example, application code could be stuck in an interrupt service that
contains a watchdog feed. Setting the window such that this would result in an early feed
will generate a watchdog event, allowing for system recovery.
The Watchdog consists of a fixed divide-by-four prescaler and a 24-bit counter which
decrements every clock cycle. The minimum value from which the counter decrements is
0xFF. Setting a value lower than 0xFF causes 0xFF to be loaded in the counter. Hence the
minimum Watchdog interval is (T
(T
following manner:
When the Watchdog Timer is configured so that a watchdog event will cause a reset and
the counter reaches zero, the CPU will be reset, loading the stack pointer and program
counter from the vector table as in the case of external reset. The Watchdog time-out flag
(WDTOF) can be examined to determine if the Watchdog has caused the reset condition.
The WDTOF flag must be cleared by software.
When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will
occur when the counter matches the value defined by the WARNINT register.
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the system clock (see
The WDCLK is used for the watchdog timer counting and is derived from the wdt_clk in
Figure
watchdog oscillator. The clock source is selected in the WDCLKSEL register
but note that the clock source may be locked by software through the MODE register.
There is some synchronization logic between these two clock domains. When the MOD
and TC registers are updated by APB operations, the new value will take effect in 3
WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog timer is
WDCLK clock cycles, the synchronization logic will first lock the value of the counter on
WDCLK and then synchronize it with the PCLK for reading as the TV register by the CPU.
•
•
•
•
•
•
WDCLK
Set the Watchdog timer constant reload value in TC register.
Setup the Watchdog timer operating mode in MOD register.
Set a value for the watchdog window time in WINDOW register if windowed operation
is required.
Set a value for the watchdog warning interrupt in the WARNINT register if a warning
interrupt is required.
Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register.
The Watchdog must be fed again before the Watchdog counter reaches zero in order
to prevent a watchdog event. If a window value is programmed, the feed must also
occur after the watchdog counter passes that value.
3. Two clocks can be used as a clock source for wdt_clk clock: the IRC and the
× 2
24
× 4) in multiples of (T
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
WDCLK
WDCLK
× 256 × 4) and the maximum Watchdog interval is
× 4). The Watchdog should be used in the
UM10441
© NXP B.V. 2011. All rights reserved.
(Table
Figure
279 of 442
269),
3).