OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 397

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OM13008,598

Manufacturer Part Number
OM13008,598
Description
BOARD LPC XPRESSO LPC122X
Manufacturer
NXP Semiconductors
Series
LPCXpressor
Datasheets

Specifications of OM13008,598

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-6642
OM13008
NXP Semiconductors
UM10441
User manual
25.4.5.5.2 Operation
25.4.5.5.3 Restrictions
25.4.5.5.4 Condition flags
25.4.5.5.5 Example
25.4.5.6.1 Syntax
25.4.5.6 MULS
The MOV instruction copies the value of Rm into Rd.
The MOVS instruction performs the same operation as the MOV instruction, but also
updates the N and Z flags.
The MVNS instruction takes the value of Rm, performs a bitwise logical negate operation
on the value, and places the result into Rd.
In these instructions, Rd, and Rm must only specify R0-R7.
When Rd is the PC in a MOV instruction:
Remark: Though it is possible to use MOV as a branch instruction, ARM strongly
recommends the use of a BX or BLX instruction to branch for software portability.
If S is specified, these instructions:
Multiply using 32-bit operands, and producing a 32-bit result.
MULS Rd, Rn, Rm
where:
Rm is a register.
imm is any value in the range 0-255.
Rd is the destination register.
Rn, Rm are registers holding the values to be multiplied.
Bit[0] of the result is discarded.
A branch occurs to the address created by forcing bit[0] of the result to 0. The T-bit
remains unmodified.
update the N and Z flags according to the result
do not affect the C or V flags.
MOVS R0, #0x000B
MOVS R1, #0x0
MOV
MOVS R3, #23
MOV
MVNS R2, R0
All information provided in this document is subject to legal disclaimers.
R10, R12
R8, SP
Rev. 1.1 — 10 March 2011
; Write value of 0x000B to R0, flags get updated
; Write value of zero to R1, flags are updated
; Write value in R12 to R10, flags are not updated
; Write value of 23 to R3
; Write value of stack pointer to R8
; Write inverse of R0 to the R2 and update flags
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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