OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 428

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 154. Fractional Divider setting look-up table . . . . .154
Table 155. UART Transmit Enable Register (TER - address
Table 156. UART RS485 Control register (RS485CTRL -
Table 157. UART RS-485 Address Match register
Table 158. UART RS-485 Delay value register (RS485DLY -
Table 159. UART FIFO Level register (FIFOLVL - address
Table 160. UART1 pin description . . . . . . . . . . . . . . . . . .160
Table 161. Register overview: UART0 (base address:
Table 162. UART Receiver Buffer Register (RBR - address
Table 163. UART Transmitter Holding Register (THR -
Table 164. UART Divisor Latch LSB Register (DLL - address
Table 165. UART Divisor Latch MSB Register (DLM -
Table 166. UART Interrupt Enable Register (IER - address
Table 167. UART Interrupt Identification Register (IIR -
Table 168. UART Interrupt Handling . . . . . . . . . . . . . . . .165
Table 169. UART FIFO Control Register (FCR - address
Table 170. UART Line Control Register (LCR - address
Table 171. UART Line Status Register (LSR - address
Table 172. UART Scratch Pad Register (SCR - address
Table 173. Auto-baud Control Register (ACR - address
Table 174: UART IrDA Control Register (ICR - 0x4000 C024)
Table 175: IrDA Pulse Width . . . . . . . . . . . . . . . . . . . . . .174
Table 176. UART Fractional Divider Register (FDR - address
Table 177. Fractional Divider setting look-up table . . . . .177
Table 178. UART Transmit Enable Register (TER - address
Table 179. UART FIFO Level register (FIFOLVL - address
Table 180. I
Table 181. Register overview: I
Table 182. I
UM10441
User manual
0x4000 8028) bit description . . . . . . . . . . . . .152
0x4000 8030) bit description . . . . . . . . . . . . .155
address 0x4000 804C) bit description . . . . .155
(RS485ADRMATCH - address 0x4000 8050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .156
address 0x4000 8054) bit description. . . . . . .156
0x4000 8058, Read Only) bit description . . . .158
0x4000 C000) . . . . . . . . . . . . . . . . . . . . . . . . .161
0x4000 C000 when DLAB = 0, Read Only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .162
address 0x4000 C000 when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . .162
0x4000 C000 when DLAB = 1) bit description 163
address 0x4000 C004 when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .163
0x4000 C004 when DLAB = 0) bit
description
address 0x4004 C008, Read Only) bit description
0x4000 C008, Write Only) bit description . . . .166
0x4000 C00C) bit description . . . . . . . . . . . .167
0x4000 C014, Read Only) bit description . . .168
0x4000 C01C) bit description . . . . . . . . . . . . .170
0x4000 C020) bit description . . . . . . . . . . . . .170
bit description . . . . . . . . . . . . . . . . . . . . . . . . .173
0x4000 C028) bit description . . . . . . . . . . . . .175
0x4000 C030) bit description . . . . . . . . . . . . .178
0x4000 C058, Read Only) bit description . . . .178
0000)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
2
2
C-bus pin description. . . . . . . . . . . . . . . . . .182
C Control Set register (CONSET - address
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
. . . . . . . . . . . . . . . . . . . . . . . . . .163
2
C (base address 0x4000
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Table 183. I
Table 184. I
Table 185. I
Table 186. I
Table 187. I
Table 188. I2SCLL + I2SCLH values for selected I2C_PCLK
Table 189. I
Table 190. I
Table 191. I
Table 192. I
Table 193. I
Table 194. CONSET used to configure Master mode. . . 191
Table 195. CONSET used to configure Slave mode. . . . 193
Table 196. Abbreviations used to describe an I
Table 197. CONSET used to initialize Master Transmitter
Table 198. CONSET used to initialize Slave Receiver
Table 199. Master Transmitter mode . . . . . . . . . . . . . . . 207
Table 200. Master Receiver mode . . . . . . . . . . . . . . . . . 208
Table 201. Slave Receiver mode . . . . . . . . . . . . . . . . . . 209
Table 202. Slave Transmitter mode . . . . . . . . . . . . . . . . 211
Table 203. Miscellaneous States . . . . . . . . . . . . . . . . . . 212
Table 204. SSP pin descriptions . . . . . . . . . . . . . . . . . . . 224
Table 205. Register overview: SSP (base address 0x4004
Table 206. SSP Control Register 0 (CR0 - address
Table 207. SSP Control Register 1 (CR1 - address
Table 208. SSP Data Register (DR - address 0x4004 0008)
Table 209. SSP Status Register (SR - address 0x4004 000C
Table 210. SSP Clock Prescale Register (CPSR - address
Table 211. SSP Interrupt Mask Set/Clear register (IMSC -
Table 212. SSP Raw Interrupt Status register (RIS - address
Table 213. SSP Masked Interrupt Status register (MIS
Table 214. SSP interrupt Clear Register (ICR - address
0x4000 0000) bit description . . . . . . . . . . . . . 183
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
0x4000 000C) bit description . . . . . . . . . . . . . 186
address 0x4000 0010) bit description . . . . . . 186
0x4000 0014) bit description . . . . . . . . . . . . . 186
values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
0x4000 0018) bit description . . . . . . . . . . . . . 187
0x4000 001C) bit description . . . . . . . . . . . . . 188
0x4000 0020, ADR2 - 0x4000 0024, ADR3 -
0x4000 0028) bit description . . . . . . . . . . . . . 189
0x4000 002C) bit description . . . . . . . . . . . . . 190
MASK1 - 0x4000 0034, MASK2 - 0x4000 0038,
MASK3 - 0x4000 003C) bit description . . . . . 190
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
0x4004 0000) bit description . . . . . . . . . . . . . 225
0x4004 0004) bit description . . . . . . . . . . . . . 226
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 227
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 227
0x4004 0010) bit description . . . . . . . . . . . . . 228
address 0x4004 0014) bit description . . . . . . 228
0x4004 0018) bit description . . . . . . . . . . . . . 229
-address 0x4004 001C) bit description . . . . . 229
2
2
2
2
2
2
2
2
2
2
C Status register (STAT - 0x4000 0004) bit
C Data register (DAT - 0x4000 0008) bit
C Slave Address register 0 (ADR0-
C SCL HIGH Duty Cycle register (SCLH -
C SCL Low duty cycle register (SCLL -
C Control Clear register (CONCLR -
C Monitor mode control register (MMCTRL -
C Slave Address registers (ADR1 -
C Data buffer register (DATA_BUFFER -
C Mask registers (MASK0 - 0x4000 0030,
Chapter 26: Supplementary information
UM10441
© NXP B.V. 2011. All rights reserved.
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