OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 304

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
20.5.2.1 Information block
20.5.2.2 Erase operations for the flash block
20.5.2.3 Write operations for the flash block
The flash memory area also contains a flash information block starting at address
0x0004 0200 with a total size of 3 pages (see
the user for storing variables, configuration parameters, and other user-defined data.
A read access by the CPU at the information block address returns the data contained in
this location. Pages in the information block can be erased by issuing the IAP command
“Erase info page”, which is specific to the information block. The IAP “Copy RAM to flash”
command then can be used to write new user data to the information block.
ISP and IAP commands allow to prepare one or more sectors for erase operations and to
erase those sectors.
In addition, the IAP commands include a page erase command, which allows erasing a
range of pages in the user flash memory regardless of sector boundaries.
On the LPC122x, the erase time increases with the number of pages or sectors to be
erased. If all sectors of the flash area are selected to be erased, the ISP and IAP routines
automatically use a more efficient “mass erase” procedure, which shortens the erase time
significantly. For details on the flash timing parameters, see the LPC122x data sheet.
Write-to-flash operations using the ISP and IAP “Copy RAM to flash” commands enable
the user code to write to flash. The minimum write size is 4 bytes, equivalent to one flash
word. The total programming time is proportional to the number of flash words written.
However, writing a whole row of 32 flash words or 128 bytes at a time is more efficient.
The “Copy RAM to flash” commands automatically detect row aligned addresses and use
a more efficient write procedure to achieve shorter row programming times.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Figure
Chapter 20: LPC122x Flash ISP/IAP
52). This flash area is available to
UM10441
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