OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 412

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
Fig 72. IPR register
25.5.2.6 Interrupt Priority Registers
25.5.2.7 Level-sensitive and pulse interrupts
IPR7
IPR
IPR0
31
The IPR0-IPR7 registers provide an 2-bit priority field for each interrupt. These registers
are only word-accessible. See the register summary in
Each register holds four priority fields as shown:
Table 380. IPR bit assignments
See
array, which provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt M as follows:
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
Bits
[31:24]
[23:16]
[15:8]
[7:0]
PRI_(4n+3)
•
•
PRI_31
PRI_3
the corresponding IPR number, N, is given by N = N DIV 4
the byte offset of the required Priority field in this register is M MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
Section 25–25.5.2.1
Name
Priority, byte offset 3
Priority, byte offset 2
Priority, byte offset 1
Priority, byte offset 0
24 23
All information provided in this document is subject to legal disclaimers.
PRI_(4n+2)
Rev. 1.1 — 10 March 2011
PRI_30
PRI_2
for more information about the access to the interrupt priority
Function
Each priority field holds a priority value, 0-3. The lower the
value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:6] of each field, bits
[5:0] read as zero and ignore writes.
16 15
Chapter 25: LPC122x Appendix ARM Cortex-M0
PRI_(4n+1)
PRI_29
PRI_1
Table 25–374
8 7
PRI_(4n)
PRI_28
PRI_0
for their attributes.
UM10441
© NXP B.V. 2011. All rights reserved.
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