OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 161

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 161. Register overview: UART0 (base address: 0x4000 C000)
[1]
UM10441
User manual
Name
RBR
THR
DLL
DLM
IER
IIR
FCR
LCR
-
LSR
-
SCR
ACR
ICR
FDR
-
TER
-
FIFOLVL
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
RO
Access Address
RO
WO
R/W
R/W
R/W
WO
R/W
-
RO
-
R/W
R/W
R/W
R/W
-
R/W
-
RO
offset
0x000
0x000
0x000
0x004
0x004
0x008
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034 -
0x054
0x058
Description
Receiver Buffer Register. Contains the next received character
to be read.
Transmit Holding Register. The next character to be transmitted
is written here.
Divisor Latch LSB. Least significant byte of the baud rate
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider.
Divisor Latch MSB. Most significant byte of the baud rate
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider.
Interrupt Enable Register. Contains individual interrupt enable
bits for the 7 potential UART interrupts.
Interrupt ID Register. Identifies which interrupt(s) are pending.
FIFO Control Register. Controls UART FIFO usage and modes. 0x00
Line Control Register. Contains controls for frame formatting
and break generation.
Reserved
Line Status Register. Contains flags for transmit and receive
status, including line errors.
Reserved
Scratch Pad Register. Eight-bit temporary storage for software. 0x00
Auto-baud Control Register. Contains controls for the
auto-baud feature.
IrDA Control Register. Enables and configures the IrDA mode.
Fractional Divider Register. Generates a clock input for the
baud rate divider.
Reserved
Transmit Enable Register. Turns off UART transmitter for use
with software flow control.
Reserved
FIFO Level register. Provides the current fill levels of the
transmit and receive FIFOs.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 10: LPC122x UART1
UM10441
0x00
0x00
0x00
-
Reset
value
NA
NA
0x01
0x00
0x00
0x01
0x00
0x60
0x00
0x10
0x80
-
0x00
© NXP B.V. 2011. All rights reserved.
[1]
Notes
when
DLAB=0
when
DLAB=0
when
DLAB=1
when
DLAB=1
when
DLAB=0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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