OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 215

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.10.8.1 Initialization
11.10.8.2 I
11.10.8.3 The state service routines
11.10.8.4 Adapting state services to an application
11.10.8 I
The I
a master or an addressed slave. When a bus error is detected, the I
switches to the not addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 0x00. This status code may be used to
vector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in
This section provides examples of operations that must be performed by various I
service routines. This includes:
In the initialization example, the I
For each mode, a buffer is used for transmission and reception. The initialization routine
performs the following functions:
The I
Call. If the General Call or the own slave address is detected, an interrupt is requested
and STAT is loaded with the appropriate state information.
When the I
26 state services to be executed.
Each state routine is part of the I
The state service examples show the typical actions that must be performed in response
to the 26 I
associated state services can be omitted, as long as care is taken that the those states
can never occur.
In an application, it may be desirable to implement some kind of time-out during I
operations, in order to trap an inoperative bus or a lost service routine.
2
2
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•
•
•
•
•
C interrupt service
C state service routines
Initialization of the I
I
The 26 state service routines providing support for all four I
The ADR registers and MASK registers are loaded with values to configure the part’s
own slave address(es) and the General Call bit (GC)
The I
The slave mode is enabled by simultaneously setting the EN and AA bits in CON and
the serial clock frequency (for master modes) is defined by loading the
registers.
2
2
2
C Interrupt Service
C hardware only reacts to a bus error when it is involved in a serial transfer either as
C hardware now begins checking the I
2
2
C interrupt enable and interrupt priority bits are set
2
C state codes. If one or more of the four I
C interrupt is entered, STAT contains a status code which identifies one of the
The master routines must be started in the main program.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
2
C block after a Reset.
2
2
C interrupt routine and handles one of the 26 states.
C block is enabled for both master and slave modes.
2
C-bus for its own slave address and General
Chapter 11: LPC122x I2C-bus controller
2
C operating modes are not used, the
Table
203.
2
C operating modes.
2
C block immediately
UM10441
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SCLH and SCLL
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C
C state