OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 204

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.10.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see
the MASK registers must be configured.
The values on the four ADR registers combined with the values on the four MASK
registers determines which address(es) the I
are enabled. See sections
Section 11.7.10
Table 198. CONSET used to initialize Slave Receiver mode
The I
to logic 1 to enable the I
acknowledge its own slave address or the General Call address. STA, STO, and SI must
be reset.
When the ADR, MASK, and CON registers have been initialized, the I
it is addressed by its own slave address followed by the data direction bit which must be
“0” (W) for the I
and the W bit have been received, the serial interrupt flag (SI) is set and a valid status
code can be read from STAT. This status code is used to vector to a state service routine.
The appropriate action to be taken for each of these status codes is detailed in
The slave receiver mode may also be entered if arbitration is lost while the I
the master mode (see status 0x68 and 0x78).
If the AA bit is reset during a transfer, the I
to SDA after the next received data byte. While AA is reset, the I
respond to its own slave address or a General Call address. However, the I
monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate the I
Bit
Symbol
Value
Figure
2
C-bus rate settings do not affect the I
7
-
-
24). To initiate the slave receiver mode, CON register, the ADR registers, and
2
All information provided in this document is subject to legal disclaimers.
C block to operate in the slave receiver mode. After its own slave address
for details.
6
I2EN
1
Rev. 1.1 — 10 March 2011
2
C block. The AA bit must be set to enable the I
Section
5
STA
0
11.9.2,
4
STO
0
2
Section
C block will return a not acknowledge (logic 1)
2
C block in the slave mode. I2EN must be set
2
C block will respond to when slave functions
Chapter 11: LPC122x I2C-bus controller
11.9.3,
3
SI
0
Section
2
AA
1
2
C block from the I
2
C block does not
11.7.8, and
2
UM10441
-
-
1
C block waits until
© NXP B.V. 2011. All rights reserved.
2
C block to
2
2
C-bus is still
C block is in
Table
0
-
-
2
204 of 442
C-bus.
201.