OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 267

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
14.7.13 Rules for single edge controlled PWM outputs
Table 248: PWM Control Register (PWMC, 0x4001 8074 (CT32B0) and 0x4001 C074 (CT32B1))
Note: When the match outputs are selected to perform as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to
zero except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to one to enable the timer reset when the timer value matches the value of the
corresponding match register.
Bit
3
31:4
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
3. If a match value larger than the PWM cycle length is written to the match register, and
4. If a match register contains the same value as the timer reset value (the PWM cycle
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
Fig 41. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and
(timer is set to zero) unless their match value is equal to zero.
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
the PWM signal is HIGH already, then the PWM signal will be cleared with the start of
the next PWM cycle.
length), then the PWM output will be reset to LOW on the next clock tick after the
timer reaches the match value. Therefore, the PWM output will always consist of a
one clock tick wide positive pulse with a period determined by the PWM cycle length
(i.e. the timer reload value).
timer goes back to zero and will stay HIGH continuously.
Symbol
PWMEN3
-
MAT3:0 enabled as PWM outputs by the PWCON register.
bit description
PWM2/MAT2
PWM1/MAT1
PWM0/MAT0
All information provided in this document is subject to legal disclaimers.
Value
0
1
Rev. 1.1 — 10 March 2011
0
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
Description
PWM mode enable for channel3. Note: It is
recommended to use match channel 3 to set the PWM
cycle.
CT32Bi_MAT3 is controlled by EM3.
PWM mode is enabled for CT132Bi_MAT3.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
41
65
(counter is reset)
100
MR2 = 100
MR1 = 41
MR0 = 65
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
NA