OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 344

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.7.5.3 Control data configuration
Remark: The controller does not write to this memory location.
Table 344. dst_data_end_ptr bit assignments
For each DMA transfer, the channel_cfg memory location provides the control information
for the controller.
At the start of a DMA cycle, or 2
word from SRAM memory. After the controller performs 2
updated channel_cfg word in SRAM.
The controller does not support a dst_size value that is different from the src_size value. If
the controller detects a mismatch in these values, it uses the src_size value for source
and destination, and when it next updates the n_minus_1 field, it also sets the dst_size
field to the same value as the src_size field.
After the controller completes the N transfers, it sets the cycle_ctrl field to 000 to indicate
that the channel_cfg data is invalid. At this point, the channel configuration is overwritten
in SRAM. This prevents the controller from repeating the same DMA transfer.
Remark: The controller updates the channel control data structure in SRAM after each
arbitration.
Bit
31:0
Name
dst_data_end_ptr
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
Description
Pointer to the end address of the destination data
R
DMA transfer, the controller fetches the channel_cfg
R
, or N, transfers, it stores the
UM10441
© NXP B.V. 2011. All rights reserved.
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