OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 322

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
20.8.6 Read Boot code version number
20.8.7 Compare <address1> <address2> <no of bytes>
20.8.8 Reinvoke ISP
Table 312. IAP Read Boot Code version number command
Table 313. IAP Compare command
Table 314. IAP Reinvoke ISP
Command
Input
Return Code
Result
Description
Command
Input
Return Code
Result
Description
Command
Input
Return Code
Result
Description
Read boot code version number
Command code: 55 (decimal)
Parameters: None
CMD_SUCCESS |
Result0: 2 bytes of boot code version number in ASCII format. It is to be
interpreted as <byte1(Major)>.<byte0(Minor)>
This command is used to read the boot code version number.
Compare
Command code: 56 (decimal)
Param0(DST): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param1(SRC): Starting flash or RAM address of data bytes to be compared. This
address should be a word boundary.
Param2: Number of bytes to be compared; should be a multiple of 4.
CMD_SUCCESS |
COMPARE_ERROR |
COUNT_ERROR (Byte count is not a multiple of 4) |
ADDR_ERROR |
ADDR_NOT_MAPPED
Result0: Offset of the first mismatch if the Status Code is COMPARE_ERROR.
This command is used to compare the memory contents at two locations.
The result may not be correct when the source or destination includes any
of the first 512 bytes starting from address zero. The first 512 bytes can be
re-mapped to RAM.
Reinvoke ISP
Command code: 57 (decimal)
None
None.
This command is used to invoke the boot loader in ISP mode. It maps boot
vectors, sets PCLK = CCLK, configures UART0 pins RXD0 and TXD0, resets
counter/timer CT32B1 and resets the U0FDR (see
may be used when a valid user program is present in the internal flash memory
and the PIO0_12 pin is not accessible to force the ISP mode.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 20: LPC122x Flash ISP/IAP
Table
153). This command
UM10441
© NXP B.V. 2011. All rights reserved.
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