OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 50

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
4.8 Deep-sleep mode details
UM10441
User manual
4.7.4.3 Wake-up from Deep power-down mode
4.8.1 IRC oscillator
4.8.2 Using external pins to wake up from Deep-sleep mode (start logic 0)
Remark: The WAKEUP pin must be pulled HIGH externally before entering Deep
power-down mode.
Waking up from Deep power-down mode causes the microcontroller to reset (see
Section
conserved. The LPC122x can wake up from Deep power-down mode in two ways (see
Section
Remark: The RESET pin has no functionality in Deep power-down mode.
The IRC is the only oscillator on the LPC122x that can always shut down glitch-free.
Therefore it is recommended that the user switches the clock source to IRC before the
microcontroller enters Deep-sleep mode.
The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM
core. The port pins PIO0_0 to PIO0_11 are connected to the start logic and serve as
wake-up pins. The user must program the start logic 0 registers for each input to set the
appropriate edge polarity for the corresponding wake-up event. Furthermore, the
interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 11 in
the NVIC correspond to 12 PIO pins (see
The start logic does not require a clock to run because it uses the input signals on the
enabled pins to generate a clock edge. Therefore, the start logic signals should be cleared
(see
The start logic can also be used in Active mode to provide a vectored interrupt using the
LPC122x’s input pins.
2. Store data to be retained in the general purpose registers
3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register
4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in
5. Use the ARM WFI instruction.
•
•
the PDRUNCFG register before entering Deep power-down mode.
Pulling the WAKEUP pin LOW wakes up the LPC122x from Deep power-down. The
minimum pulse width for the HIGH-to-LOW transition on the WAKEUP pin is 50 ns.
An RTC interrupt (if it is not masked in the RTCIMSC register, see
up the LPC122x from Deep power-down mode.
Table
4.6). However, the contents of the RTC registers and the backup registers are
4.9):
39) before use.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 4: LPC122x System control (SYSCON)
Section
4.5.30).
(Table
57).
UM10441
Table
© NXP B.V. 2011. All rights reserved.
(Table
259) wakes
386).
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