F84045 Asiliant Technologies, F84045 Datasheet - Page 103

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.9.9. Cache Mode and Initialization
Cache "enabled" means that the cache is operating normally, performing line fills and cache hits as needed. Before
enabling the L2 cache, software must first initialize it. "Cache initialize" means filling the entire cache with valid cache
lines (data and tags) and making sure the cache contents remain valid at the time the cache is finally enabled.
Initialization is accomplished by setting the cache to "Initialize" mode and reading a block of DRAM equal in size to
the sum of L1 and L2 cache sizes. Reading a 640KB block of DRAM is sufficient to initialize all cache sizes except
1MB.
Disabling a writeback cache also requires special care. A WT cache can be disabled anytime, but a WB cache that has
been in the "Enabled" condition may contain the only valid copy of certain DRAM data. The data in the cache must be
flushed, i.e., written back out to DRAM, before disabling the cache. This can be accomplished by reading a block of
DRAM equal in size to TWICE the sum of L1 and L2 cache sizes. Reading a 640KB block of DRAM is sufficient to
flush all cache sizes except 512KB and 1MB.
The secondary cache may be switched from "Disabled" to "Initialize mode" or vice versa at any time. Cache
initializing and flushing is explained in more detail below.
To facilitate initialization of the cache and disabling of the cache, the following cache control bits have been defined.
Revision 1.0
WRMODE
ENCACHE
INITCACHE
cycles update the cache data and tag as normal. No castouts are performed. Write hits are handled as write
through. ENCACHE should be a 0 when this mode is being used.
FRZCDIR
No updates on cache miss. No castouts occur either. Write hits still update the cache and dirty bit. Read hits
come from cache. This mode emulates direct static RAM. It may be used in either write through or write back
mode.
Table 5.14: Cache Modes.
2/10/95
encache
0
0
0
0
1
1
1
1
1
1
Write Mode. Selects the write-hit policy.
Enable Cache.
Initialize cache. All read cycles are forced to be read misses. All cacheable memory read
Freeze cache directory
frzcdir
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
0
1
initcache wrmode
Subject to change without notice
0
1
0
1
0
0
1
0
0
1
Write through
Write back
Disable cache
Enable cache
Normal operation
Initialize cache mode
Normal cache operation
No directory update.
X
X
X
X
X
X
0
1
0
1
102
Cache off (default).
Initialize cache. Writes forced write thru.
Cache off
Nothing useful.
Normal Cache operation, write through
Normal Cache operation, write back
Invalid
Directory Frozen, write through.
Directory Frozen, write back.
Invalid.
Mode
Preliminary
Functional Description
CS4041