F84045 Asiliant Technologies, F84045 Datasheet - Page 7

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

6. 84045 Functional Description ...................................................................................................142
Revision 1.0
5.11. ISA Bus ................................ ................................ ................................ ................................ .................. 115
5.12. Fast IDE ................................ ................................ ................................ ................................ ................. 116
5.13. Multifunction Pins ................................ ................................ ................................ ................................ .123
5.14. Power Management ................................ ................................ ................................ ................................ 125
5.15. Internal Keyboard/Mouse Controller ................................ ................................ ................................ .....136
5.16. Manufacturing Test Modes ................................ ................................ ................................ .................... 141
6.1. SIPC Chip Overview ................................ ................................ ................................ ................................ 142
6.2. Clocks ................................ ................................ ................................ ................................ ...................... 143
6.3. Reset ................................ ................................ ................................ ................................ ........................ 144
6.4. GATEA20 ................................ ................................ ................................ ................................ ................ 146
6.5. Arbitration ................................ ................................ ................................ ................................ ................ 146
5.11.1. CPU or VL Master Accesses to the ISA Bus ................................ ................................ ......... 115
5.11.2. DMA or ISA Master Accesses to the ISA Bus ................................ ................................ ......116
5.11.3. DMA or ISA Master Accesses to DRAM or VL Slaves ................................ ........................ 116
5.12.1. Connections and Signal Generation ................................ ................................ ...................... 117
5.12.2. Cycle Description ................................ ................................ ................................ .................. 118
5.12.3. Software Considerations ................................ ................................ ................................ ........ 122
5.13.1. CPU Functions ................................ ................................ ................................ ...................... 123
5.13.2. Cache and DRAM Functions ................................ ................................ ................................ .123
5.13.3. VL-Bus Functions ................................ ................................ ................................ ................. 123
5.13.4. SMM and Power Management Functions ................................ ................................ ............. 123
5.13.5. Chip Selects and I/Os, & Misc ................................ ................................ .............................. 124
5.13.6. Pin Selection ................................ ................................ ................................ .......................... 124
5.14.1. Power Management Techniques ................................ ................................ ............................ 125
5.14.2. SMI Sources ................................ ................................ ................................ .......................... 128
5.14.3. SMI Timing Modes ................................ ................................ ................................ ............... 129
5.14.4. Activity Monitor Timers ................................ ................................ ................................ ........ 129
5.14.5. Wake Up Events ................................ ................................ ................................ .................... 131
5.14.6. Events Detection ................................ ................................ ................................ .................... 131
5.14.7. I/O Restart ................................ ................................ ................................ ............................. 133
5.14.8. Power Management Clock Changing ................................ ................................ .................... 134
5.15.1. Host CPU Commands ................................ ................................ ................................ ........... 137
6.1.1. 4045 Added Features ................................ ................................ ................................ ............... 142
6.1.2. Using 4045 in place of 4035 ................................ ................................ ................................ ...143
6.1.3. A quick design checklist. ................................ ................................ ................................ ......... 143
6.2.1. 14.31818 MHz clock ................................ ................................ ................................ ............... 143
6.2.2. SCLK................................ ................................ ................................ ................................ .......144
6.2.3. DMA and Refresh clock generation. ................................ ................................ ....................... 144
6.2.4. 32.768KHz clock ................................ ................................ ................................ ..................... 144
6.3.1. Inhibiting IPC Reset for 0V Suspend ................................ ................................ ...................... 145
6.5.1. Arbitration Overview ................................ ................................ ................................ ............... 146
6.5.2. VL Master Arbitration ................................ ................................ ................................ ............. 146
6.5.3. Main Arbitration Logic ................................ ................................ ................................ ............ 147
2/10/95
Subject to change without notice
5
Preliminary
Table of Contents
CS4041