F84045 Asiliant Technologies, F84045 Datasheet - Page 21

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

ISA Bus
BALE
MEMR#
MEMW#
IOR#
IOW#
IOCHRDY
0WS#
MEMCS16#
IOCS16#
Address
BE0:3#
SBHE#
XA0:1
A2:9
A10:16
A17:23
Revision 1.0
117
109
108
116
115
91
90
89
93
160, 159, 158, 157
107
106, 105
195, 194, 193, 192, 191, 185, 184, 183
182, 181, 180, 177, 176, 175, 174
173, 172, 171, 169, 168, 167, 166
2/10/95
OUT
I/O
I/O
I/O
I/O
I/O
IN
I/O
IN
I/O
I/O
IN
I/O
IN
Buffered Address Latch Enable. Direct drive of the ISA bus.
Memory Read Strobe. Direct drive of the IS A bus. Output when HLDA or LGNT#
Memory Write Strobe. Direct drive of the ISA bus. Output when HLDA or LGNT#
I/O Read Strobe. Direct drive of the ISA bus. Output when HLDA or LGNT# are
I/O Write Strobe. Direct drive of the ISA bus. Output when HLDA or LGNT# are
ISA bus ready. Output when an I SA slave (DMA and ISA master accesses to local
ISA bus Zero wait state signal. An ISA bus slave will drive this signal low when a
Output when an ISA slave (DMA and ISA master accesses to local DRAM or local
Input for CPU or local master accesses to the ISA bus.
Byte enables. Input for CPU or local master accesses to the ISA bus. Output for
ISA Bus BHE#. Output for CPU or local master accesses to the ISA bus. Input for
I/O Output for CPU or local master accesses to the ISA bus. Input for DMA or ISA
Local Bus Address bus. Always inputs.
Local Bus Address bus. Output for DMA cycles. A10:16 of the DMA address is
Local Bus Address bus. Always inputs.
are low. Input when they are both high.
are low. Input when they are both high.
low. Input when they are both high.
low. Input when they are both high.
DRAM or local bus slaves). Open collector. Input for CPU or local master
accesses to the ISA bus.
memory command falls to force a 0 wait state cycle. It may also be used to force
a 2 wait state cycle for 8 bit memory or I/O.
bus slaves). Open collector. Input for CPU or local master accesses to the ISA
bus.
DMA or ISA master cycles. Generated from XA0:1 and SBHE#.
DMA or ISA master cycles.
master cycles.
sent on XD0:6 from the 4045 and latched in the 4041.
Subject to change without notice
20
Preliminary
Pin Descriptions
CS4041