F84045 Asiliant Technologies, F84045 Datasheet - Page 141

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Clocking during a transmission is always provided by the keyboard or mouse, not by the controller, regardless of
whether the transmission is to or from the controller. When the keyboard and mouse are both idle and enabled for
input to the host, the clock and data lines for each device are both high. To inhibit transmission, the clock is held
continuously low for as long as transmission is to be inhibited. The clock and data lines have open collector drivers in
the controller, keyboard and mouse. External pull-up resistors keep the signals in the logic high state when not being
driven low.
The typical sequences of events for data transmission are summarized below.
Both the keyboard and the mouse use the same protocol, as described above. Clock timing during all transmissions is
determined by the keyboard or mouse, typically around 40 us low and 40 us high.
The controller is largely transparent to the content of transmissions to or from the keyboard or mouse. The main
processing done by the controller, other than serial-to-parallel conversion (or vice versa), is to translate keyboard scan
codes as required by PS/2 standards.
5.15.1.1.1. Additional Considerations
External 8042. The default following reset is for the internal keyboard controller to be enabled (mouse disabled). See
Index 39h. This is necessary with certain keyboards in systems that use the internal keyboard controller. These
keyboards need the clock line held in the low state following system reset. If an external keyboard controller is used,
the clock and data outputs from the 4041 need to be reprogrammed as inputs from the external controller. During the
time before the BIOS can enable these pins as inputs, the 4041 will be driving them low at the same time that the
external controller is trying to drive them high. To limit the current that can flow during this time, 1K ohm series
resistors should be used between the 4041 KBCLK/KBDATA pins and the external controller's GATE A20 and CPU
RESET pins.
Revision 1.0
Input to controller from device:
Output from controller to device:
Device waits for its clock and data lines both to be high.
Device asserts the start bit (data line driven low).
Upon seeing the device's start bit, the controller drives the other device's clock line low to inhibit transmissions
The transmitting device pulses its clock line low 11 times, driving the next data bit onto the data line after each
After the 11th clock pulse, the controller typically drives the clock low as long as needed to make the input
When the controller is ready to accept new input, the controller releases the clocks to both devices, allowing
Controller drives both clock lines low, inhibiting transmissions from both the keyboard and the mouse.
If the controller needs to transmit to the keyboard, the controller holds the mouse clock low continuously
After both clocks have been low for a period of time, the controller releases the clock to the receiving device.
Some time after detecting the controller's start bit, the receiving device pulses the clock line low 11 times. The
During the 11th clock pulse (while the clock is low and the stop bit is being sent), the device drives the data
When the controller is ready to accept new input from the other device, it releases the other device's clock line.
from the other device while the first device is transmitting.
rising edge of the clock. Data transitions during input to the controller occur while the clock is high.
data available for reading by the host CPU.
the clocks to return high.
throughout the transmission. (Vice versa for transmission to the mouse.)
At about the same time, the controller begins driving the start bit (0) onto the data line.
controller drives the next data bit onto the data line shortly after each falling edge of the clock. Data
transitions during output from the controller occur while the clock is low, usually very near the falling edge
of the clock.
line low to signal the "line control" bit to the controller. The device releases the data line after releasing the
clock at the end (rising edge) of the 11th clock pulse.
2/10/95
Subject to change without notice
140
Preliminary
Functional Description
CS4041