F84045 Asiliant Technologies, F84045 Datasheet - Page 94

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.9.3. SRAM Requirements
The 4041 cache controller uses standard off the shelf SRAMs for both tag and data.
Either 1 or two banks of Data RAMs are supported. If two banks are installed they are word interleaved, which puts
less timing constraints on the RAM speed (allowing slower RAMs to be used, or a faster cache mode to be used).
Revision 1.0
2/10/95
A4:n
A4:n
SRAMs with 2 CE pins
CCS (from 4041)
W/R#
BE0#
BE1#
BE2#
BE3#
Figure 5.3: Cache RAM Low Power Option Connections
A0-N
CE
OE
WE
A0-N
CE
OE
WE
A0-N
CE
OE
WE
A0-N
CE
OE
WE
CCS is a multifunction pin which may be either active high or active low.
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
8 bit tag
11 bit tag
F08
VCC
Figure 5.4: Cache Tag RAM Connections
Subject to change without notice
TAG0
TAG1
TAG2
TAG3
TAG4
TAG5
TAG6
TAG7
TAG8
TAG9
TAG10
TAG0
TAG1
TAG2
TAG3
TAG4
TAG5
TAG6
TAG7
TAG8
TAG9
TAG10
4041
4041
A0
A1
A2-N
CE1
CE2
OE
WE
A0
A1
A2-N
CE1
CE2
OE
WE
A0
A1
A2-N
CE1
CE2
OE
WE
A0
A1
A2-N
CE1
CE2
OE
WE
TAGWE
TAGWE
CWEA
CWEB
CWEA
CWEB
CRDA
CRDB
CRDA
CRDB
CA3A
CA3B
CA3A
CA3B
D0-7
D0-7
D0-7
D0-7
CA2
CA2
CCS (from 4041)
W/R#
BE0#
BE1#
BE2#
BE3#
93
A4:n
8 bit tag, write through only
A4:n
Tag 0 is the dirty bit, and may be left unconnected
SRAMs with 1 CE pin
F00
if write through will be used exclusively.
A0-N
CE
OE
WE
A0-N
CE
OE
WE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D0
D1
D2
D3
D4
D5
D6
D7
9 bit tag
VCC
VCC
F00
TAG0
TAG1
TAG2
TAG3
TAG4
TAG5
TAG6
TAG7
TAG8
TAG9
TAG10
TAG0
TAG1
TAG2
TAG3
TAG4
TAG5
TAG6
TAG7
TAG8
TAG9
TAG10
4041
4041
A0
A1
A2-N
CE
OE
WE
A0
A1
A2-N
CE
OE
WE
A0
A1
A2-N
CE
OE
WE
A0
A1
A2-N
CE
OE
WE
TAGWE
TAGWE
CWEA
CWEB
CWEA
CWEB
CRDA
CRDB
CRDA
CRDB
CA3A
CA3B
CA3A
CA3B
CA2
CA2
D0-7
D0-7
D0-7
D0-7
Preliminary
Functional Description
CS4041