F84045 Asiliant Technologies, F84045 Datasheet - Page 43

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
20
Revision 1.0
Index
20
0
1
2
3
5:4
7:6
cache mode cache read1 cache read0 cache write1 cache write0 cache enable
Function
Bits
Cache Controller Mode.
dual-bank secondary cache in writeback mode, or 03h for cache initialization.
WRMODE Write Mode. Selects the write-hit policy. Never change the state of this bit while bit 3 is
INITCACHE Initialize cache. All cacheable memory read cycles update the cache. No castouts are
FRZCDIR Freeze cache directory (intended for diagnostic testing)
Cache Enable. 0 (default) = disable cache. 1 = enable cache.
Cache write timing mode
Cache read timing mode
2/10/95
'1'.
performed. Write-hit cycles are executed as write through. This bit should never be changed
from '0' to '1' unless bit 3 is '0' or is changed to '0' at the same time. While this bit is '1', bit 0 has
no effect. Similarly, bit 3 should not be changed from '0' to '1' unless bit 1 is '0' or is changed to
'0' at the same time.
Never change this bit from '0' to '1' without initializing the cache first. Also, if bit 0 is '1', never
change bit 3 from '1' to '0' without performing a cache flush first.
0
1
0
1
0
1
00
01
10
11
00
01
10
11
D7
Description
Write through
Write back (preferred for highest performance)
Cache responds to read hits
Read hits are disabled.
Normal cache operation
No directory update.
2-1-1-1 burst write (for typical cache configurations)
(Reserved)
3-2-2-2 burst write (for single-bank and slow SRAM)
4-2-2-2 burst write
2-1-1-1 bursts (for typical cache configurations)
2-2-2-2 bursts (for single-bank and slow SRAM)
3-2-2-2 bursts
(Reserved)
D6
Subject to change without notice
D5
Default = 00. Typical setting = 09h for normal operation with a
42
D4
D3
frzcdir
D2
initcache
Configuration Registers
Preliminary
D1
wrmode
D0
CS4041