F84045 Asiliant Technologies, F84045 Datasheet - Page 72

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

4.5. Co-processor Logic
The co-processor logic is in the 4045 chip. It has pins for FERR# and IGNNE#. IRQ13 is generated internally. A
write to I/O ports F0 or F1 clears the interrupt. The FERR# and IGNNE# pins may be converted to IRQ13 and
INTCLR# respectively to allow external coprocessor error logic to be used.
For further information, see Section 6.12.
4.6. ISA Bus and ISA Features
CPU and local master accesses to the ISA bus are handled by the 4041 Chip. The 4045 is an ISA slave at that time.
The 4045 contains the DMA controllers, and becomes the master for DMA cycles, and provides the arbitration for ISA
masters. The 4041 is an ISA slave at that time, and converts ISA cycles to local bus cycles for local DRAM, cache, and
local bus slaves.
For further information, see Sections 5.5.1, 5.11, 6.8, and 6.10.
Other ISA compatible features:
4.7. Local Bus Support
The CS4041 CHIPSet fully supports the VL-Bus 2.0. Both local bus slaves and masters are supported with very little
external logic. Below is a brief description of the VL-Bus support. Refer to the individual chip specs for more details:
4041 Chip:
4045 Chip:
For further information, see Sections 4.3, 5.5, 5.11, and 5.13.
4.8. DRAM controller
The DRAM controller supports 8 banks. This is configured as 4 blocks which may each contain 1 or 2 banks. This
allows 4 double bank SIMMs to be installed. A "bank" is defined as a dword-wide physical memory controlled by a
single RAS signal. The 4041 provides a total of 8 RAS lines, one for each bank. A single set of four CAS lines
provides individual byte write control in each bank.
Each block has a programmable DRAM size, number of banks installed (1 or 2), and starting address. This allows
maximum flexibility in DRAM installation, and does not require that banks be installed in any particular physical
order.
Revision 1.0
Performance control using HOLD
Standard IPC functions and 4045 enhancements
16-bit I/O decoding
Port 61h and Speaker output
Samples LDEV# at the start of each bus cycle (either the end of the first or second T2) and allows a local bus
Translates DMA and ISA master cycles to local bus cycles when LDEV# is active.
Allows local masters to access most all of the system resources as if they are the CPU.
Provides 1, 2, or 3 sets of LREQ# and LGNT# signals for local bus masters.
slave to capture the cycle if active.
Performs snooping of the CPU L1 write back cache when enabled.
Takes the CPU out of HOLD to write back a modified cache line.
2/10/95
see Section 6.11.
see Sections 3.2, 3.4, and 6.14.
Subject to change without notice
see Section 6.6.
see Section 6.9.
71
System Level Functions
Preliminary
CS4041