F84045 Asiliant Technologies, F84045 Datasheet - Page 36

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

3.3. 84041 Index Configuration Registers
Note: Various suggestions for programming the Configuration Registers are included in the register descriptions. The
following bits are affected by the CPU type; refer to the respective bit descriptions for specific programming
suggestions:
Index
05
06
Revision 1.0
Index 38h bits 0, 1, 2.
Index 8Dh bits 3 through 7.
Index 93h bit 7.
Index 94h bits 0, 1, 3, 4.
Index
Index
06
05
1:0
3:2
5:4
7:6
1:0
3:2
5:4
6
7
ISA cmd dly
Function
Function
ISA wait
state
Bits
ISA bus command delays
Two bits for each cycle type.
I/O cycle command delay. Default is 1.
8 bit memory command delay Default is 1.
16 bit memory command delay Default is 0.
(Reserved). Write 0s.
ISA bus Wait States, Address hold.
(Reserved)
8 bit AT bus wait states
16 bit AT bus wait states
(Reserved).
AT bus address hold time (ready delayed by an extra clock after the AT command goes inactive).
2/10/95
00
01
10
11
00
01
10
11
00
01
10
11
0
1
add hold
D7
D7
-
Description
0 BCLK delay (command active at falling edge of ALE - default for 16 bit memory).
1 BCLK delay (default for all cycles except 16 bit memory).
2 BCLK delay
3 BCLK delay
5 BUSCLK wait states (default)
4 BUSCLK wait states.
3 BUSCLK wait states.
2 BUSCLK wait states.
3 BUSCLK wait states (default)
2 BUSCLK wait states.
1 BUSCLK wait states.
0 BUSCLK wait states.
no additional hold time (default)
additional hold time.
D6
D6
-
-
Subject to change without notice
16b m dly
16b wait1
D5
D5
Default = 05. Typical setting = 05.
16b m dly0
16b wait0
35
D4
D4
Default = 00. Typical setting = 24h.
8b m dly1
8b wait1
D3
D3
8b m dly0
8b wait0
D2
D2
IO dly1
Configuration Registers
Preliminary
D1
D1
-
IO dly0
D0
D0
-
CS4041