F84045 Asiliant Technologies, F84045 Datasheet - Page 60

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
94
95
96
Revision 1.0
index
index
index
94
95
96
0
1
2
3
4
5:7
0
1
5
6
7
7:0
smm modes
Shadow70
I/O restart
function
function
function
Bits
SMM modes.
This register controls the SMM modes of the CPU.
SMIACT3 / SMIADS# mode
Force FLUSH on SMM.
Force A20M# on SMM.
Disable KEN# on SMM.
Soft redirection.
(Reserved, write as ‘000’)
I/O Restart selection.
This register selects which I/O ports cause an I/O restart. A 1 in the bit position causes that range to
generate an I/O restart cycle. I/O restart means that the 4041 asserts SMI during a CPU I/O cycle,
which the CPU recognizes as an I/O restart SMI. The CPU then enters SMM with status information
allowing the SMM routine to determine what I/O resource is being addressed. The SMM routine
performs peripheral power-up and re-initialization as needed, then exits SMM, allowing the CPU to
re-execute the same I/O operation that caused the SMI. This register should always be set to ‘00h’ if
Index 92h bit 4 is ‘0’. Otherwise, cycle timing may malfunction during I/O to an enabled range.
COM1 (3F8:3FF)
COM2 (2F8:2FF)
2
3
4
Keyboard (60 & 64)
Programmable I/O range 0
Programmable I/O rang e 1
Port 70 shadow register.
This register provides a means of reading back the last value written to port 70h, including the NMI
enable bit, which would otherwise be unreadable. This register is read only. Do not write to this
register.
Port 70 shadow read.
2/10/95
prog IO 1
port70d7
0
1
0
1
0
1
0
1
0
1
D7
D7
D7
Description
SMIACT# function (Intel method)
SMIADS# function (Cyrix method)
Do not flush the CPU cache upon entry into SMM
Flush the CPU cache by pulsing FLUSH# when SMIACT# goes low. This should
SMM has no effect on A20M#
Drive A20M# high with SMIACT#
SMM has no effect on KEN#
Drive KEN# high for all SMM accesses.
Do not redirect soft resets.
Disable soft resets and redirect to SMI.
LPT2 (378:37F)
Floppy and hard disk (1F0:1F7, 3F0:3F1, 3F3:3F5, 170:177, 370:377)
VGA I/O (3B0:3BB, 3C0:3DF)
prog IO 0
port70d6
only be done with an Intel CPU. It need not be done when the SMM windows
below 1M are not used.
D6
D6
D6
Subject to change without notice
port70d5
KB
D5
D5
D5
SoftResRedir
port70d4
59
VGA
D4
D4
D4
floppy/HD
port70d3
DisKen
D3
D3
D3
ForceA20m flushOnSmm
LPT(378)
port70d2
D2
D2
D2
port70d1
com2
Configuration Registers
Preliminary
D1
D1
D1
smiact pin
port70d0
com1
D0
D0
D0
CS4041