F84045 Asiliant Technologies, F84045 Datasheet - Page 24

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Interrupts
IOCHCK#
NMI
SMI#
INTR
Control Link & Keyboard
LIN
LOUT
KBDATA/GATEA20
KBCLK / KBRESET#
MDATA
MCLK
Multifunction Pins
GPIOA
GPIOB
GPIOC
GPIOD
VCC, GND
VCC
GND
Revision 1.0
70
72
73
71
82
83
94
95
102
101
1
4
103
208
(8 pins)
(15 pins)
2/10/95
IN
I/O
OUT
IN
IN
OUT
I/O
I/O
I/O
I/O
IN
OUT
OUT
OUT
Parity error indicator from the ISA bus. Generates an NMI and sets the IOCHCK#
NMI to the CPU. Generated for DRAM parity errors and when IOCHCK# has gone
System Management Interrupt. Output of the power management logic.
CPU INTR pin from the 4045. Used to detect system events. Specifically used to
Control Link input from the 4045. Transfers the following information: Port B bit
Control Link output to the 4045.
Keyboard data to internal keyboard controller. If the internal keyboard controller is
Keyboard clock to the internal keyboard controller.
Mouse data to internal 8042.
Mouse clock to internal 8042.
Multifunction pin. Always an input.
Multifunction pin. Always an output.
Multifunction pin. Always an output.
Multifunction pin. Always an output.
13, 34, 49, 69, 96, 133, 170, 202
3, 18, 28, 40, 60, 74, 75, 88, 126, 127, 144, 147, 178, 179, 206
flag.
low. Each of these has enable bits plus a final mask. This pin is also sampled at
the end of SYSRESET (falling edge) to determine whether the 4041 will operate
in 1X clock mode (pin pulled up) or 2X mode (pin pulled down).
restart the CPU clock when it has been stopped.
5, Refresh Request, Refresh Complete, Address Strobe.
Acknowledge cycle, CPU Reset Request, Refresh Acknowledge, and keyboard
interrupt (from internal keyboard controller).
disabled, this signal becomes the Gate A20 signal from the external 8042. The
4041 detects transitions on this pin and transmits them to the 4045 over the
control link.
controller is disabled, this signal becomes the CPU reset from the external 8042.
When this signal goes low, the 4041 sends a code across the control link to
inform the 4045 of this. The 4045 will perform the CPU reset (restart).
Subject to change without notice
23
Transfers the following information: Interrupt
If the internal keyboard
Preliminary
Pin Descriptions
CS4041