F84045 Asiliant Technologies, F84045 Datasheet - Page 6

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5. 84041 Functional Description .....................................................................................................75
Revision 1.0
4.13. CPU Capabilities for Power Management ................................ ................................ ............................... 74
5.1. DRAM/Cache/ISA Controller Chip ................................ ................................ ................................ ........... 75
5.2. Clocks ................................ ................................ ................................ ................................ ........................ 75
5.3. Reset and GATEA20 ................................ ................................ ................................ ................................ . 76
5.4. Arbitration ................................ ................................ ................................ ................................ ................. 78
5.5. Address Mapping ................................ ................................ ................................ ................................ ....... 78
5.6. SMM Memory Support ................................ ................................ ................................ ............................. 84
5.7. CPUs Supported ................................ ................................ ................................ ................................ ........ 86
5.8. CPU Write Back Cache Snooping ................................ ................................ ................................ ............. 89
5.9. Secondary Cache Controller ................................ ................................ ................................ ...................... 90
5.10. DRAM Controller ................................ ................................ ................................ ................................ .. 106
4.13.1 CPU Clock Control ................................ ................................ ................................ .................. 74
4.13.2 System Management Mode (SMM) ................................ ................................ ......................... 74
5.2.1. Clock Generating Logic ................................ ................................ ................................ ............ 75
5.2.2. Clock Inputs ................................ ................................ ................................ .............................. 76
5.3.1. CPU Reset and SMI ................................ ................................ ................................ .................. 76
5.3.2. Emulated 8042 KBRESET# and GATEA20 ................................ ................................ ............. 77
5.5.1. I/O Addressing ................................ ................................ ................................ .......................... 78
5.5.2. Memory Addressing ................................ ................................ ................................ .................. 80
5.6.1. 4041 SMM Memory Map Details ................................ ................................ ............................. 84
5.6.2. Additional 4041 SMM Features ................................ ................................ ................................ 85
5.7.1. CPU SMM Differences ................................ ................................ ................................ ............. 87
5.7.2. CPU Clock Differences ................................ ................................ ................................ ............. 87
5.7.3. CPU L1 Cache Options ................................ ................................ ................................ ............. 87
5.7.4. CPU Pin Connections ................................ ................................ ................................ ............... 87
5.9.1. Pin Usage ................................ ................................ ................................ ................................ .. 91
5.9.2. External Connections ................................ ................................ ................................ ................ 92
5.9.3. SRAM Requirements ................................ ................................ ................................ ................ 93
5.9.4. Cacheability ................................ ................................ ................................ .............................. 95
5.9.5. Write Protection ................................ ................................ ................................ ........................ 96
5.9.6. Cache RAM Power-Down ................................ ................................ ................................ ........ 97
5.9.7. Cache Coherency ................................ ................................ ................................ ...................... 97
5.9.8. Cache Operation ................................ ................................ ................................ ........................ 98
5.9.9. Cache Mode and Initialization ................................ ................................ ................................ 102
5.9.10. Tag & Data SRAM Testing ................................ ................................ ................................ ... 104
5.10.1. Block Decodes ................................ ................................ ................................ ...................... 107
5.10.2. Address Muxing ................................ ................................ ................................ .................... 110
5.10.3. Timing Modes ................................ ................................ ................................ ....................... 111
5.10.4. DRAM Refresh ................................ ................................ ................................ ..................... 113
5.10.5. DRAM Parity ................................ ................................ ................................ ........................ 113
5.10.6. Alternate Master Accesses (VL or ISA Master, or DMA) ................................ ..................... 113
5.10.7. Programming the Timing Modes. ................................ ................................ .......................... 114
5.10.8. Automatic DRAM Sizing & Setup ................................ ................................ ......................... 115
2/10/95
Subject to change without notice
4
Preliminary
Table of Contents
CS4041