F84045 Asiliant Technologies, F84045 Datasheet - Page 160

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

6.10. Address Buffers
The SIPC drives all of its address lines for DMA cycles and some of its address lines for refresh cycles. It also drives
SA17:19 for all except master and master refresh cycles.
6.11. Internal IO Decode and configuration register access.
6.11.1. Configurations Registers.
The SIPC is allocated index registers 01, and 08 to 0Fh. 08, 09, and 0Ah are implemented in the 4035. 0Bh and 0Ch
are added for the 4045 for the superset functions. 01 is inside the IPC core.
The index registers are accessed through ports 22 and 23. 22 is a write only address register, and 23 is a read/write data
port. The address of the register is first written to 22, then the data is read from or written to port 23. Port 22 must be
written before each access to 23.
The 4045 adds the ability for SMM code to access the configuration registers through ports 26 and 27. This is required
to prevent the SMM code from splitting a port 22/23 access by user code. The index value is stored separately for ports
22 and 26, and there is a separate “accessed” flag for 26/27.
6.11.2. IO decodes.
IO decoding is done from SA0:7 and A8:9. The 4045 decodes the following IO:
A full list of ports and their functions is given in Section 3.
Revision 1.0
CPU or Local Master cycles. SA0:7 and A8:9 are address inputs for IO cycles. SA17:19 are driven from
A17:19. All other SIPC address lines are floated and not used.
DMA cycles. SIPC address utilization during DMA is described in the DMA Controllers section.
ISA Master cycles. All address lines are floated. A0:9 are inputs, and are used for IO decode.
Hidden Refresh. SA0:7 are driven with the refresh address. This address is incremented following each
refresh cycle, including master refreshes. SA17:19 are driven from the DMA Page Register (bits 1:3), which
will normally be low (they are programmable). All other address lines are floated.
Master Refresh. As far as SPIC address lines are concerned, this is the same as Hidden Refresh except for
SA17:19, which are floated.
CPU Snooped Write Back. When WBACK# goes low, A8:9 and A17:23 are floated if they are being driven.
WBACK# may go low when any device owns the bus, but the SIPC is only affected during DMA cycles, since
that is when A8:9 and A17:23 are driven.
IPC ranges
Port 22/23 and 26/27 for configuration registers
Port 60h for resetting the mouse interrupt
Port 61h (also known as “Port B”)
Port 92h
Ports F0h & F1h for the numeric coprocessor error reset
2/10/95
Subject to change without notice
159
Preliminary
Functional Description
CS4041