F84045 Asiliant Technologies, F84045 Datasheet - Page 142

no-image

F84045

Manufacturer Part Number
F84045
Description
Manufacturer
Asiliant Technologies
Datasheet

Specifications of F84045

Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
F84045
Manufacturer:
CHIPS
Quantity:
1 831
Emulated Gate A20 and CPU Reset. The emulation option (Index 39h) for Gate A20 and CPU reset is most useful
when using an external 8042, to provide a significant performance benefit over normal 8042 processing delays. The
emulation options are also usable with the internal keyboard/mouse controller, providing a slight performance
advantage over the internal controller. For highest system performance, the emulation option should always be
enabled, regardless of whether the internal or external keyboard/mouse controller is being used.
5.16. Manufacturing Test Modes
The 4041 has two test modes to support board-level manufacturing test:
The same basic procedure is used for activating either of these modes:
In the connectivity test mode, all pins except SYSRESET, TEST#, and ROMCS# become inputs to an AND-gate tree.
The final output of the AND is ROMCS#. When all inputs are high, ROMCS# is high. When any pin is driven low,
ROMCS# goes low.
To exit from test mode, pulse SYSRESET while TEST# (4041 LIN pin) remains high. Keep SYSRESET high for at
least 5 cycles of SCLK.
Revision 1.0
Putting all outputs in a high-impedance state (Hi-Z)
Checking each pin's soldering connection (AND tree)
Drive SYSRESET high for at least 5 cycles of SCLK. (SCLK must be running or pulsed.)
While SYSRESET is high, drive TEST# low (4041 LIN pin).
While TEST# is low, drive SYSRESET low. Allow at least 3 cycles of SCLK from falling edge of TEST# to falling
Drive a test code onto XD7:0. Use code 01h for the "Hi-Z" test mode, or 07h for the connectivity test (AND tree).
Keep TEST# low and XD7:0 valid for at least 5 cycles of SCLK after SYSRESET goes low.
Drive TEST# high. The rising edge of TEST# latches the test code into the 4041. XD7:0 should remain valid for at
edge of SYSRESET.
least 20 ns after TEST# is driven high.
2/10/95
Subject to change without notice
141
Preliminary
Functional Description
CS4041

Related parts for F84045