F84045 Asiliant Technologies, F84045 Datasheet - Page 31

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Table 3.2: 84041 and 84045 Configuration Register Summary
Indexes
01
05
06
07
08
09
0A
0B
0C
0D-0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25-27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
Revision 1.0
4041
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
2/10/95
4045
X
X
X
X
X
X
-
Description
IPC DMA controller wait states, clock.
ISA bus command delays
ISA bus wait states, address hold.
ISA bus clock selection
Performance Control
4045 Misc. Control
DMA Clock selection.
VL Arbitration and WBACK# control
Port 92 and RTC feature control
(Reserved - for 4045)
DRAM Timing
DRAM Setup
DRAM Configuration, blocks 0 & 1
DRAM Configuration, blocks 2 & 3
DRAM block 0 Starting Address
DRAM block 1 Starting Address
DRAM block 2 Starting Address
DRAM block 3 Starti ng Address
Video shadow and local bus control.
DRAM shadow read enable.
DRAM shadow write enable.
ROMCS enable.
SMM Shadow RAM enable.
DRAM Block Parity Enable & Flash ROM shadow enable
Secondary DRAM Timing register
(Reserved) for Secondary Timing Select Register.
Cache Controller Mode
Cache Controller Configuration
Cache Testing Control
Data port for tag testing, bits 0:7
Data port for tag testing, bits 8:10
(Reserved)
I/O Decode #0 Address Low.
I/O Decode #0 Address High.
I/O Decode #0 Size and Mask.
I/O Decode #0 Configuration.
I/O Decode #1 Address Low.
I/O Decode #1 Address High.
I/O Decode #1 Size and Mask.
I/O Decode #1 Configuration.
Memory Decode #0 Address Low.
Memory Decode #0 Address High.
Memory Decode #0 Size and Destination.
Memory Decode #0 Attributes.
Memory Decode #1 Address Low.
Memory Decode #1 Address High.
Memory Decode #1 Size and Destination.
Memory Decode #1 Attributes.
Subject to change without notice
30
Preliminary
Registers
CS4041