F84045 Asiliant Technologies, F84045 Datasheet - Page 98

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

With writeback caches, memory reads and writes can result in updated data being loaded into the cache while the
memory area of origin is enabled for writing. Updated data may still be present in the cache at the time that the
memory area is changed to write disabled. Sometime later, the updated data may need to be written back out to
memory after the memory (shadow RAM) has become write disabled. This is not a problem for L2 cache because the
writeback operation is initiated and controlled by the 4041, which performs the L2 writeback regardless of whether or
not the DRAM has become write protected. DRAM write protection prevents line fills, cache writes, and normal
DRAM writes, but does not prevent L2 writeback operations when needed.
For L1 cache in the CPU, however, there is no way for the 4041 to know that a CPU writeback operation is occurring,
since the CPU initiates and controls the cycle. The writeback will fail if the memory area has become write protected.
To avoid this problem, the system should set Index 18h bit 6 to ‘1’ to force writes to shadow RAM to be write-through
rather than write-back in L1 cache. Making L1 cache write-through causes all writes to appear on the CPU pins,
allowing the 4041 to perform the DRAM write while the DRAM is still write enabled, or to assert EADS# (Index 18h
bit 7 set to ‘1’) if the DRAM has become write protected.
5.9.6. Cache RAM Power-Down
Many cache RAMs go into a power-down mode when their chip selects are inactive. Since cache RAMs consume a
significant amount of power, it may be advantageous to power them down between bus cycles, since the 486 CPU only
uses the bus about 50% of the time (DX2 uses the bus a higher percentage of the time).
The cache controller provides a chip select pin for this function, which may be optionally used. When cache RAMs
with only 1 chip select are used, the chip select must be gated with the byte enable and W/R# logic.
The chip select goes low asynchronously with ADS#, and stays low until the cache controller no longer requires use the
cache RAMs. For a cycle where the cache is involved (a hit or line fill) the chip select will go high at the end of the
final T state. For ISA bus or VL-Bus cycles it will go high when the cache determines that the cycle is a miss and is
non-cacheable. For back to back cache cycles the chip select will be high for only a short time.
5.9.7. Cache Coherency
Coherency must be maintained in the primary and secondary caches when VL masters, ISA masters, and DMA cycles
occur. Cache Coherency is handled in several ways:
Revision 1.0
Secondary cache: Coherency is maintained by always writing the data in the cache on write hits, regardless of
the current master. There are no valid bits in the tag, so every cache location must be valid at all times after
initialization. Coherency on reads is maintained by always reading the data out of the cache on read hits, to
prevent stale data from being read from the DRAM. This is required because the secondary cache is write
back.
486 Primary cache . Coherency is maintained by driving EADS# low for all local master, ISA master, and
DMA memory writes (VL-Masters are responsible for driving it when they own the bus). This invalidates the
cache line in the 486. The address is already provided on the local bus. A24:31 are driven low when ISA
masters and the DMA controller have the bus (A28-30 have pull downs at the 486 since they do not go to the
4041).
486 Primary Write Back cache: Any access to DRAM must snoop the primary cache before accessing either
the secondary cache or the DRAM. This is done by driving EADS# low and waiting for the HITM# signal
before returning any READYs from the DRAM or cache controller. If dirty data is found in the cache, the
current local bus cycle is backed off (by removing either the VL-master or the 4041 itself from the bus) and the
CPU is taken out of hold and allowed to write back. The local bus cycle is then reissued. The line in the CPU
is invalidated.
2/10/95
Subject to change without notice
97
Preliminary
Functional Description
CS4041