F84045 Asiliant Technologies, F84045 Datasheet - Page 96

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.9.4. Cacheability
Only local DRAM is cacheable in either the 486 or secondary cache. Shadow RAM (RAM at 640-1M when present) is
optionally cached. The programmable memory decodes may also make areas non-cached. If the total local DRAM
size exceeds the cacheable range for the selected L2 cache size and tag width, DRAM above the cacheable range is
automatically non-cacheable in L2 (high-order CPU address bits must be zero to get a cache hit or line fill). The entire
DRAM is still cacheable in CPU cache (L1).
The 4041 controls L1 cacheability by driving KEN# low (cacheable) or leaving it high (non-cacheable) as needed.
(The default is high.) The following Index bits affect KEN# usage and L1 cacheability:
Other bits can affect cacheability indirectly by enabling or disabling DRAM. As noted above, local DRAM is usually
always cacheable in both L1 and L2 unless specifically made non-cacheable, and memory accesses outside local
DRAM are never cacheable in L2 but might be cacheable in L1 if specifically enabled using Indexes 33h or 37h (see
Section 5.5.2.1).
Note that KEN# controls the L1 cache line fill decision, NOT the L1 cache hit/miss decision. Cacheability is controlled
by not allowing line fills. Once information has been put into the cache and not invalidated by flush or EADS#, hits
and writebacks can occur regardless of whether or not the memory area of origin may have been changed to non-
cacheable status after the information was cached.
Likewise, L2 cacheability is controlled in the line fill decision, NOT in the cache hit/miss decision. (Write protected
shadow RAM results in L2 cache writes being inhibited during attempts to write to the protected area.) As with L1
cache, information already in the L2 cache can result in cache hits and writebacks even if the memory area of origin has
been changed to non-cacheable status.
The following Index bits affect L2 cacheability apart from other bits that enable or disable local DRAM:
Index 22h bits 7:6 determine whether the cache is an instruction cache, a data cache, or both. The standard
configuration is caching both. The other options allow performance tests to be performed. Restricting the cache to
code or data affects only cache line fills, which occur only during read misses. For instance, if the cache is set for data
only and a read miss occurs during a code fetch, it is treated as non-cacheable and the cache line is not replaced. If the
existing line contains dirty data, it is not written back, since it is not being replaced.
Read and write hits are not affected by these bits, since they must continue to occur for proper cache coherency. For
instance: The cache is set for data only and write back. A line fill occurs on a data read, followed by a write to the line,
causing the cache line to become dirty. If a subsequent code fetch occurs to this same location, it must be read from the
cache since that is the only valid copy. The same memory areas will be used for both code and data (Code generally
gets loaded into the memory from which it is executed with prior Data write cycles).
Revision 1.0
Index 18h, bit 2 (shadow RAM) and bit 7 (write protection).
Indexes 33h and 37h, bits 0 and 1 (memory decodes).
Index 94h, bit 3 (SMM).
Index 18h bit 3 (shadow RAM).
Index 22h, bits 7 and 6 (see below).
2/10/95
Subject to change without notice
95
Preliminary
Functional Description
CS4041