F84045 Asiliant Technologies, F84045 Datasheet - Page 135

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.14.8. Power Management Clock Changing
There are many CPU types and modes for slowing and stopping the clock. Consequently, there are many ways for this
CHIPSet to slow down and stop the clock. The CS4041 is fairly flexible with the switching and stopping, allowing
individual functions to be selected based on the CPU and mode being used, rather than setting the CPU type and mode
in a register. An endless variation of CPUs and modes seems inevitable. The individual functions will be described,
followed by what CPUs and CPU modes require what.
When to Slow Down the Clock
Either method may be used to slow the clock down. A TimerA time-out is optional, and normally used with a non-
SMM CPU, or when SMM is not to be used for this function. TimerA may be programmed to time-out after a
specified amount of system inactivity. The Software Command would normally be used from within SMM, but is
available at any time.
When to Speed Up the Clock
WakeA goes active on any selected event. In the software power management mode this would generate an SMI which
would switch the clock.
How to slow down the Clock
If the internal divider is used, it is preset to a slow down frequency and the hardware or software command switches to
that divider. For standard 486 CPUs, a synthesizer may be used, which will change the clock frequency gradually
enough to meet the requirements of the CPU's VCO. The 4041 then simply provides an output pin to switch to slow
mode. The internal divider is not used.
When to stop the Clock
The clock may be set to stop when a HALT CPU bus cycle is detected. It may also be set to only do this when the slow
clock is running. This would allow a very low power 'green' mode without affecting normal full speed operation. The
system would wake up on each timer tick and the clock is then stopped by executing a HALT at the end of the timer
tick routine or in higher-level power management routine that originally executed the first HALT. A software
command may also be used, but the HALT method will probably be used in SMM mode instead.
Revision 1.0
LDEV# (internal)
TimerA
Software command
WakeA
Software command
Internal Divider
Signal to external synthesizer
Halt bus cycle
Halt bus cycle only while slow clock is running
Software command
2/10/95
ADS#
SMI#
RDY#
T1
Figure 5.19: I/O Restart Timing
Subject to change without notice
(Software Power Management)
(Software Power Management)
134
(Hardware Power Management)
(Hardware Power Man agement)
T1
Preliminary
Functional Description
CS4041