F84045 Asiliant Technologies, F84045 Datasheet - Page 59

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
90
91
92
93
Revision 1.0
index
90
91
92
93
0
1
2
3
4
5
6
7
0
1
2
3
7:4
0
1
2
3
4
5
6
7
0
1
2
3
6:4
7
smi EnableB
SMI statusA next register
SMI statusB
smi enableA global enable
function
Bits
SMI Status Register 0
This register indicates what events are currently causing an SMI. The bit will be a 1 if it is currently
pulling SMI low. Writing a 1 to a bit location resets that bit (except for bit 7).
TimerA Timeout
TimerB Timeout
WakeA Event
WakeB Event
I/O Restart
Halt cycle
(Reserved).
Any bit in SMI status Register 1.
SMI Status Register 1
Additional SMI sources. The bit will be a 1 if it is currently pulling SMI low. Writing a 1 to a bit
location resets that bit. The OR of the bits in this register appear in bit 7 of the SMI Status Register 0.
Software SMI
CPU restart request.
External SMI 0
External SMI 1
(Reserved)
SMI Enable Register 0
This register enables SMI sources. 0 disables, 1 enables.
TimerA Timeout
TimerB Timeout
WakeA Event
WakeB Event
I/O Restart
Halt cycle
(Reserved).
Global SMI enable bit. Disables all SMI sources if 0. SMM routines should set this bit to 0 and then
SMI Enable Register 1
Additional SMI enables.
Software SMI
CPU restart request.
External SMI 0 (EXT0 pin)
External SMI 1 (EXT1 pin)
(Reserved)
SMI# Mode
2/10/95
back to 1 again before leaving SMM, to guarantee an edge on the SMI# pin if any SMI sources
are still active. Otherwise, the CPU may fail to return to SMM in response to the active source.
(This is not necessary if no other sources are active, indicated by reading 00h in Index 90h.)
smi mode
0
1
D7
-
Description
Intel Mode
Cyrix Mode
D6
-
-
-
-
Subject to change without notice
Halt
Halt
D5
-
-
I/O Restart
I/O Restart
58
D4
-
-
WakeupB
WakeupB
External1
External1
D3
WakeupA
WakeupA
External0
External0
D2
CPU restart Software smi
CPU restart Software smi
TimerB
TimerB
Configuration Registers
Preliminary
D1
TimerA
TimerA
D0
CS4041