F84045 Asiliant Technologies, F84045 Datasheet - Page 58

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
8D
8E
8F
Revision 1.0
index
index
8D
8E
0
1
2
3
6:4
7
Writing:
0
1
2
3
7:4
Reading:
0
7:1
1:0
3:2
Commands
Stop Clock
function
function
Bits
Clock switching modes.
These bits select the clock switching and stopping modes.
Stop On Halt. 1=Stop the CPU clock on a HALT bus cycle.
Stop On Halt while Slow. 1=Stop the CPU clock on a HALT bus cycle only when the CP U clock is
Stop Clock Mode.
Pull STPCLK# when switching the CPU clock.
PLL delay. Delay between changing the clock frequency and removing STPCLK#
Wait for Stop Clock Acknowledge bu s cycle.
Software Commands and Status.
Writing to this register causes specific actions to be taken. If the bit is a 1 the action occurs. If it is a
0 no action is taken for that function. There is no actual register which holds the values written here.
Reading this register provides status information for internal hardware functions.
GoSlow command. Writing a 1 causes the clock to be slowed down by whatever means is selected.
GoFast command. Writing a 1 causes the clock to return to full speed.
Stpclk. This will cause the CPU clock to be stopped using the selected stop clock method.
Generate an SMI. Writing a 1 will generate a software SMI.
(Reserved, write as 0.)
Clock Speed. 0=slow clock, 1=full speed.
(Reserved)
External Event pin function.
EXT0 function:
EXT1 function (same bit definitions as EXT0)
7:4
2/10/95
in SLOW mode.
Bits 0 and 1 should not both be written as 1s.
00
01
10
11
waitstopack
0
1
0
1
000
001
010
011
0
1
D7
D7
Description
Pull STPCLK# only.
Pull STPCLK# and then actually stop the CPU clock.
Do not pull STPCLK# when switching the clock frequency.
Activate STPCLK# before any clock change.
No delay
32uS delay
64uS delay
128uS delay
Do no wait for the Stop Clock Acknowledge bus cycle.
Wait for Stop Clock Acknowledge before changing the clock.
Active low level triggered
Active high level triggered
Active low edge triggered (negative edge)
Active high edge triggered (positive edge)
(Reserved)
plldelay2
D6
D6
Subject to change without notice
plldelay1
D5
D5
100
101
110
111
plldelay0
57
D4
D4
256uS delay
512uS delay
1mS delay
2mS delay
stpclk4slow
GenSMI
D3
D3
stopmode
Stpclk
D2
D2
StopHaltnslo StopOnHalt
GoFast
Configuration Registers
Preliminary
D1
D1
GoSlow
D0
D0
CS4041