F84045 Asiliant Technologies, F84045 Datasheet - Page 110

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.10.1.2. Controlling Page Mode and Page Interleaving
Page Mode is automatic. Page mode is always used for CPU and Local Master initiated cycles.
controlled by the DRAM configuration bits, as discussed below.
The 4041 can perform two-way interleaving. Two banks may be interleaved if they are the same size (depth). If two
banks are installed in a block, they are automatically interleaved by virtue of the 2 banks bit being set (the two banks in
a block are required to be the same depth). Two single bank blocks may be interleaved if they are the same size, and
one is an even numbered block and the other is an odd numbered block. This is done by setting their starting addresses
to be the same and setting both interleave bits. Interleaving and non-interleaving may be mixed, and multiple sets of
banks may be interleaved. For example:
The following bank combinations may be interleaved:
The interleave scheme used in the 4041 is designed to be very versatile for the user. When a block is interleaved, its
block decode is doubled in size. The interleave bit (either A11 or A12) is included in the bank decode and decoded to
either a 0 or a 1 depending on the bank number. This makes the bank show up in every other page (2K or 4K). Table
5.20 shows what CPU address bits are used for the DRAM row address, Column address, bank decode, and the
interleave bit.
Two banks are interleaved when they both have their block starting addresses pointing to the same place and one
decodes the interleave bit to a 0 and the other one decodes it to a 1.
When both banks of a block are installed they are automatically interleaved. The interleave bit decoding was chosen
such that the two banks will always decode the interleave bit in opposite directions. When a block is programmed for
two banks the interleave bit is ignored, since interleaving is automatic. There is also only one starting address for the
block, so all that need be done is programming the block for two banks.
Two banks in different blocks may be interleaved by programming the starting addresses to be the same and setting the
interleave bit for both blocks. The DRAM depth must be the same to avoid getting a memory map which is full of
holes. It is required that one of the blocks be even numbered and one be odd numbered so that one will decode even
pages (interleave bit decoded to a 0) and one will decode the odd pages (interleave bit decoded to a 1). If both are even
the two banks will sit on top of each other on the even pages and the odd pages will be empty, and likewise if they are
both odd. A double bank block may not be interleaved with another block since it is already interleaved with itself.
The algorithm below can be used to auto configure for interleaving. A double bank block will automatically interleave
itself prior to this algorithm.
Revision 1.0
Example 1:
Example 2:
Example 3:
1 & 2
2 & 6
if block 0 & 1 are the same size & both have only 1 bank installed.
endif
if block 2 & 3 are the same size & both have only 1 bank installed.
endif
if blocks 0 & 3 are the same size, both have only 1 bank installed, and neither have been interleaved above
endif
if blocks 1 & 2 are the same size, both have only 1 bank installed, and neither have been interleaved above
endif
2/10/95
Blocks 1 and 2 have single bank 1M SIMMs (using RAS1# & RAS2# respectively) which are
Block 3 has a single bank 256K SIMM which is not interleaved with anything.
Banks 0 & 1 have 256K deep parts and be interleaved with each other.
Banks 0 & 3 have 256K deep parts and are interleaved with each other
Block 0 has a double bank 256K SIMM (using RAS0# & RAS4#) which is interleaved with
itself.
interleaved with each other.
Program blocks 0 & 1 to the same address and set both interleave bits.
Program blocks 2 & 3 to the same address and set both interleave bits.
Subject to change without notice
Bank 2 may have 1M parts, not interleaved with anything.
Bank 3 may have 4M parts, not interleaved with anything.
Banks 1 & 2 have 1M parts and are interleaved with each other.
0 & 1
2 & 3
0 & 4
3 & 7
Program blocks 0 & 3 to the same address and set both interleave bits.
Program blocks 1 & 2 to the same address and set both interleave bits.
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0 & 3
1 & 5
Preliminary
Functional Description
Page Interleaving is
CS4041