F84045 Asiliant Technologies, F84045 Datasheet - Page 153

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

6.8. ISA Bus
This section describes the generation and usage of the ISA bus control signals on the SIPC.
AEN
MASTER#
DREQ0:7, DACK0:7#, TC
MEMR#, MEMW#
SMEMR#, SMEMW#
IOR#, IOW#
6.9. IPC Functions
The 4035 and 4045 include the IPC megacell, which is basically the 82C206 chip.
“Compatible” peripherals necessary to make an AT computer. The functions are as follows:
6.9.1. DMA Controllers
The DMA controllers consist of two 8237 compatible blocks and a page register module, compatible with the
74LS612.
8237 DMA controllers are designed for 8-bit data transfer using a 16-bit address. PC/AT architecture allows 16-bit
data transfers by left-shifting one controller's address by one bit. PC/AT architecture also allows a 24-bit address by
using a 74LS612 dual-port RAM to provide the additional address bits.
Revision 1.0
This signal is driven continuously high during DMA cycles, low at all other times (including ISA Master
cycles). During DMA, AEN indicates that the address on the SA-bus is a memory address, not an I/O address,
even though IOR# or IOW# is active.
This is an input. It forces AEN continuously low during ISA Master cycles.
These come directly from the DMA logic in the IPC megacell. DREQ0:7 are inputs. DACK0:7# and TC are
always outputs.
These signals are inputs except during DMA and refresh.
SMEMW#. During refresh (either SIPC-initiated or ISA Master-initiated), MEMR# is an output from the
refresh logic. MEMW# remains an input during refresh. During DMA cycles, both signals are outputs from
the SIPC.
Always outputs, even when an ISA master has the bus. They follow MEMR# and MEMW# respectively when
the address is below 1Meg (A20-23 are all low). They are high if any of A20-23 are high. An exception to
this is when REFRESH# is low, at which time SMEMR# follows MEMR# regardless of the address.
These signals are outputs during DMA, inputs at all other times.
2 DMA controllers, 8237-compatible with page register extension.
2 Interrupt Controllers, 8259-compatible
1 Three-channel Timer, 8254-compatible
1 Real Time clock and with CMOS RAM, a superset of the Motorola 146818
2/10/95
Subject to change without notice
152
They are used to generate SMEMR# and
It includes many of the
Preliminary
Functional Description
CS4041