F84045 Asiliant Technologies, F84045 Datasheet - Page 57

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
8A
8B
8C
Revision 1.0
index
index
8A
8B
8C
2:0
3
4
7:5
7:0
2:0
3
6:4
7
timerB cntl
Time Base
function
function
timerB
Bits
TimerB Control Register
This register provides the rate and function of TimerB and the function of the WakeB Event. TimerB
may also cause an SMI. This is enabled in the SMI enable register.
TimerB count rate.
(Reserved)
Stop the CPU clock on TimerB timeout.
(Reserved)
TimerB Count Register
Writing to this register sets the count value. A value between 1 and FF may be written. This value is
reloaded in the timer each time an EventB occurs. Reading this register gives the current value of the
timer.
programmed here.
TimerB restart value.
Time Base Selection & Slow Clock frequency
This register selects the clock source and the divider necessary to make an approximately 1MHz time
base for the timer and PLL delay functions.
Divider Selection.
Clock source selection.
Slow clock divider. Specifies the divider used for the system clock when the slow mode is selected.
STPCLK# pin usage
2/10/95
No switching is actually done for the 000 setting.
stpclk pin#
With the rate set to OFF, the current value of the timer will be the restart value last
000
001
010
011
0
1
000
001
010
011
0
1
000
001
010
011
0
1
tmrB7
D7
D7
-
Description
Off.
64uS
1mS
16mS
Disabled
TimerB timing out will cause the CPU clock to be stopped. The selected Stop-Clock
Divide by 24.
Divide by 32
Divide by 40
Divide by 48
CLKIN (divided by 2 if 2x clock mode).
Multifunction pin (used for 14.31818MHz clock in).
Full speed
Divide by 2
Divide by 4
Divide by 6
STPCLK# pin is in fac t STPCLK#
STPCLK# pin is switched to the CLKSPEED pin. 1=Full Speed, 0=reduced speed.
slowclk2
tmrB6
protocol will be followed, as specified elsewhere.
May be used to control an external clock generator.
D6
D6
-
Subject to change without notice
slowclk1
tmrB5
D5
D5
-
56
Stop clk
sloclk0
tmrB4
D4
D4
100
101
110
111
100
101
11x
100
101
110
111
tmrB3
cksel
D3
D3
-
rateB2
tmrB2
div2
D2
D2
256mS
4 seconds
64 seconds
(Reserved)
Divide by 14
(Reserved)
(Reserved)
Divide by 8
(Reserved)
(Reserved)
(Reserved)
rateB1
tmrB1
Configuration Registers
div1
Preliminary
D1
D1
rateB0
tmrB0
div0
D0
D0
CS4041