F84045 Asiliant Technologies, F84045 Datasheet - Page 85

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

5.6. SMM Memory Support
5.6.1. 4041 SMM Memory Map Details
The 4041 places SMM memory anywhere in the D0000-FFFFF area, where the BIOSes reside. This has several
advantages, including:
SMM code would be in the BIOS area. In most cases it would be in the E0000 area, but it could be in the F0000 or
D0000 also. In the case of E0000 the area would probably be read-only in user space and read/write for SMM. In the
case of D0000 it would be disabled in user space.
Using D0000 effectively gives SMM it's own address space. With memory managers such as QEMM, 386max, or the
DOS 6 utilities, the C0000, D0000, and E0000 areas are checked for memory or peripherals. If nothing is found, these
programs back fill the address space with extended memory using virtual-86 mode. Some of the area is used as the
EMS page frame (if enabled) and the rest is used to load drivers high. Therefore, the addresses of D0000 or E0000
never appear on the CPU pins when in user mode after initialization, since the space is remapped. In SMM mode the
paging is not used, and the actual address of D0000 or E0000 will come out of the CPU and access the shadow RAM.
Effectively this looks like two separate sets of memory at D0000 and/or E0000.
The shadow RAM read and write registers are repeated for SMM space, and the alternate set is used on a cycle by cycle
basis with SMIACT# or SMIADS# (depending on the CPU type)
The configuration register at index 1C provides the shadow DRAM mode while in SMM. It allows separate control of
the D0000, E0000, and F0000 ranges. If all of the bits are set to 1s, the entire range from D0000-FFFFF will be
enabled as read/write shadow RAM in SMM mode. In order to access these memory ranges on the ISA bus, the
appropriate bits should be turned off. The following table shows how the shadow RAM bits interact:
If shadow RAM is enabled in both user and SMM spaces, it is the same physical memory that appears in both modes.
This allows the SMM code to be loaded from user space by enabling the shadow registers.
With the Intel CPUs the initial SMI will use the address of 38000 as the SMM base address. This is in the middle of
the bottom 1meg of user space. The base address may be changed before the return is executed, allowing all future
SMIs to vector to a new base. In the 4041, this initial SMI goes to user space. A dummy SMI should be generated,
with code at 38000 to change the base address to the desired area in the D0000-FFFFF range.
Revision 1.0
Main memory is all available at its normal address.
SMM memory may be (optionally) cached in L1 and/or L2
Allows cache to remain enabled, and no requirement to flush the CPU cache.
2/10/95
Table 5.8: User/SMM Space Shadow RAM Bits
Memory Range
D0000-DFFFF
D0000-DFFFF
C0000-CFFFF
C0000-CFFFF
E0000-EFFFF
E0000-EFFFF
F0000-FFFFF
F0000-FFFFF
Subject to change without notice
Cycle type
writes
writes
writes
writes
reads
reads
reads
reads
Reg 1A bits 0:3
Reg 19 bits 0:3
User Space bit
84
Reg 1A bit 4
Reg 1A bit 5
Reg 1A bit 6
Reg 19 bit 4
Reg 19 bit 5
Reg 19 bit 6
same as user space
same as user space
SMM Space bit
Reg 1C bit 0
Reg 1C bit 4
Reg 1C bit 1
Reg 1C bit 5
Reg 1C bit 2
Reg 1C bit 6
Preliminary
Functional Description
CS4041