F84045 Asiliant Technologies, F84045 Datasheet - Page 92

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Table 5.8.2: Cacheable Range
5.9.1. Pin Usage
The pin utilization is such that no jumpers are required on a board which offers all combinations of cache size,
interleave and non-interleave, and tag width. The exception to this is that the proper address bits must be provided to
the tag RAM based on the cache size. Since the unbuffered CPU address must go to the tag RAM for speed reasons, it
is not possible for the CHIPSet to do the switching. Unused tag bits must be pulled up because they are compared to 1
during the cache hit-miss decision process. This allows faster decision time than would be possible with added internal
logic to ignore the unused tag bits. Separate pull-ups should be used because software may drive the pins driven to
different values during tag testing, so the pins should not be shorted together.
Revision 1.0
Highest Tag Bit
A22
A23
A24
A25
A26
A27
Table 5.9: Cache Pin Usage
SRAM Pin
TAGWE#
TAG1-10
CWEA#
CWEB#
CRDA#
CRDB#
2/10/95
CA3A
CA3B
TAG0
CCS#
CA2
Pin
Maximum Cacheable
128 MB
256 MB
16 MB
32 MB
64 MB
Range
8 MB
Tag RAM write enable
Single Bank mode
Cache Chip Select
Cache RAM WE#
Cache RAM OE#
Cache RAM A2
Cache RAM A3
Subject to change without notice
unused
unused
unused
Write Back
Dirty
Tag
91
Highest Address (A15, 16, 17, 18, or
Cache Chip Select (both banks)
Even bank Cache RAM WE#
Even bank Cache RAM OE#
Odd bank Cache RAM WE#
Odd bank Cache RAM OE#
Even bank Cache RAM A3
Odd bank Cache RAM A3
Interleaved Bank mode
Tag RAM write enable
Write Through
19)
unused
Tag
Preliminary
Functional Description
CS4041