F84045 Asiliant Technologies, F84045 Datasheet - Page 69

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Index
0C
Revision 1.0
index
0C
0
1
2
3
4
5
6
7
RTC, pt92
function
Bits
Port 92 and RTC feature control.
internal KBC.
Port 92 reset disable.
Port 92 Password protect enable.
(Reserved)
CPU Reset Mode. Newer CPUs may need to be in HOLD before being reset.
CPU restart alternate code disable.
IRQ12 output enable.
(Reserved)
IPC Core Reset Disable. Prevents loss of IPC register contents during 0V suspend (system powered
2/10/95
down except for 4045; also known as "suspend to disk"). Software should set this bit to 1 before
initiating a 0V suspend sequence, so that IPC registers will be preserved during resume. When
resuming, software should write a 0 to this bit. This bit is cleared by PSRSTB# instead of
PWRGOOD.
To guarantee IPC core reset for manufacturing test or other reasons, PWRGOOD and PSRSTB#
must both be low at the same time. This condition will exist automatically if main power is off
(PWRGOOD low) and the system battery is being changed or connected for the first time
(PSRSTB# momentarily low). PSRSTB# is internally blocked (ignored) when PWRGOOD is
high.
0
1
0
1
0
1
0
1
D7
-
Description
Port 92 bit 0 causes a CPU restart.
Port 92 bit 0 restart disabled. The 4041 will handle port 92 restarts by causing an
Disable the Port 92 password protect feature. Setting this bit to a 0 will NOT re-
Enable the Port 92 password protect feature.
0
1
Link code 101 generates a CPU restart
Link code 101 does not generate a CPU restart. Must be set if this code is used for
Disabled.
The mouse interrupt flip flop drives IRQ12. It is open collector.
0
1
SMI.
enable accesses to the CMOS RAM password area if it has already been
protected.
the mouse interrupt. When used with the 4041 it may always be set to a 1 (for
the 4031 it should be a 0).
D6
-
Subject to change without notice
IRQ12 out
D5
Reset CPU only when the CPU is NOT in HOLD.
Reset the CPU only when the CPU is in HOLD.
Reset the IPC core when PWRGOOD is low.
Do not reset the IPC core when PWRGOOD is low.
link code
68
D4
Typical setting = 00h for external 8042, 30h for 4041
D3
-
D2
-
rtc password pt92 res dis
Configuration Registers
Preliminary
D1
D0
CS4041