F84045 Asiliant Technologies, F84045 Datasheet - Page 62

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Addr
61
70
Revision 1.0
0
1
2
3
4
5
6
7
0-6
7
Port
61
Bits
"Port B"
This is an AT compatible port with miscellaneous information. Bits 0-3 are read/write. Bits 4-7 are
read only. Only bits 0 to 5 are contained in the 4045 (bits 2 and 3 are there for readback purposes
only). The remainder are in the 4041. On I/O reads the 4045 drives bits 0-5 to their proper values,
and bits 6 & 7 to 0s. Default = 20h.
Timer 2 gate. This bit enables or disables the 1.19 MHz clock input to Timer 2. The output from
Speaker Data. This bit is ANDed with the output of timer 2 and inv erted to produce the signal
Enable Parity Check. 0 enables local DRAM parity checking. A 1 disables local DRAM parity
Enable IOCHCK. 0 enables the IOCHCK interrupt. A 1 disables IOCHCK and clears the IOCHCK
Refresh Detect. This read only bit toggles on each refresh. It should toggle whenever timer 1
Timer 2 output. Read only. This bit allows software to monitor the output of timer 2, which is
(Channel Check latch). This bit is not in the 4045. It is contained in the 4041. A 1 indicates that
(Parity Check latch). This bit is not in the 4045. It is contained in the 4041. A 1 indicates that a local
Real Time Clock Address Port & NMI mask.
Real Time clock address. The value written to these bits becomes the address of RTC/CMOS RAM
(NMI Mask.) This bit is not in the 4045. It is used in the 4041. This bit is inverted and ANDed with
2/10/95
Timer 2, in conjunction with bit 1 below, provides the signal for the speaker. If this bit is a 1,
Timer 2 is enabled, and (if programmed to do so) will produce a square wave of the programmed
frequency. When this bit is a 0, bit 5 below is forced to 1 and the speaker output signal will be
high or low depending on bit 1 below.
actually sent to the speaker. When the gate (bit 0 above) is low, this bit gives direct software
control of the speaker. The speaker signal will be high or low when this bit is 0 or 1, respectively.
When the speaker is idle, bits 0 and 1 normally will both be 0 and the speaker output signal will
be high.
checking and clears the local parity error flip-flop. This bit is inverted and sent to the active low
preset of a flip-flop. The Q output is PCK# and is fed to the NMI logic. A parity error clocks the
flip-flop to a 0. There is also an index register bit to block local DRAM parity errors. It prevents
the flip-flop from being clocked. The flip-flop is an F74 on the AT, where the Preset has
precedence on Q and Clear has precedence on Q#.
flip-flop. This bit is inverted and sent to the active low clear of a flip-flop. IOCHCK# is sent to
the active low Preset input. The Q# output is fed to the NMI logic. The Q output is sent to bit 6
of this register. The flip-flop is an ALS74 on the AT, where the Preset has precedence on Q and
Clear has precedence on Q#.
produces a pulse (about every 15us). This should be done even if ISA refresh is disabled. Some
software uses this as a time delay.
ANDed with bit 1 of this register and inverted to produce the speaker signal. The speaker signal
is low when bits 1 and 5 are both 1. If either bit is 0, the speaker output is high. By setting bits 1
and 0 to '01', software can use Timer 2 and bit 5 without generating any speaker output.
IOCHCK# has been activated. This bit is the Q output of the flip-flop mentioned in bit 3 of this
register. The 4045 will drive this bit to a 0 on reads.
parity error has occurred. It is the Q# output of the flip-flop mentioned in bit 2 of this register.
The 4045 will drive this bit to a 0 on reads.
which will be read or written through port 71.
the NMI sources (the OR of several sources). The result of the AND function is NMI to the CPU.
This allows the CPU "Non-Maskable Interrupt" to be maskable externally.
(Parity err)
D7
Description
(CHCK)
D6
Subject to change without notice
Tmr 2
D5
Ref Detect
61
D4
chck enable
D3
parity enab
D2
spkr data
D1
Preliminary
I/O Port Addresses
tmr2 gate
D0
CS4041