F84045 Asiliant Technologies, F84045 Datasheet - Page 89

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Subject to change without notice
Functional Description
RESET. For non-SMM CPUs, where this is the only RESET pin, it should be connected to CPURESET from the
4045. For SMM CPUs, which have an SRESET or INIT pin, the RESET pin should be connected to SYSRESET.
SRESET or INIT. If this pin exists on the CPU, it should be connected to CPURESET. This reset will not clear the
SMM base. On CPUs with a write back cache, the CPU handles it more like an interrupt to avoid corrupting the cache.
The 4041 has the ability to redirect all CPU restart requests to SMM.
BS8#. Connect to a pull-up.
BS16#. Connect to a pull-up and to each VL bus slot.
BOFF#. Tie high.
AHOLD. Tie low.
EADS#. Connect to the 4041 and all VL bus slots. VL masters will drive this pin. The 4041 drives it during DMA
and ISA Master cycles and for write protected areas.
A20M#. Connect to the 4045 A20M# pin.
FLUSH#. This signal may be provided by either the 4041 or the 4045, but generally is not required to be connected to
either. The 4041 may optionally flush the CPU cache before entering SMM, but this is not required by the SMM
memory scheme of the 4041. The 4045 may flush the cache as part of the Performance Control function, or the 4045 -
FLUSH# pin may be redefined as an additional LGNT# signal, which is probably a more common use. If FLUSH# is
not connected to either the 4041 or 4045, it should be pulled high.
L1 Write back cache pins:
HITM#. CPU output which connects to the 4041.
WBACK#. 4041 output which connects to the 4045 and all VL slots.
WB / WT#. CPU input optionally used for making selected memory areas write-through instead of write back. The
4041 can provide this signal on a multifunction pin (GPB) which defaults to this function, and the 4041 can be
programmed to make the programmable memory ranges (Index registers 30-37h) cacheable in L1 as WT only. If the
4041 pin is not used, a pull-up resistor should be provided to enable the WB mode for L1 cache.
CACHE#. CPU output, not used by the 4041 or 4045.
INV. CPU input indicating whether to invalidate the L1 cache or not when snooped. High = invalidate. May be
connected to W / R# to invalidate only on writes, or tied high.
WPROT#. CPU input found on some non-Intel CPUs. The 4041 optionally provides this signal on a multifunction
pin, which write protects the shadow RAM as specified in the configuration registers. If not used, WPROT# may float.
BLEN#. Used on the upgrade socket. Leave floating or pull high.
EWBE#. Used on the upgrade socket. External Write Buffer Empty input. Leave floating or pull high.
Revision 1.0
2/10/95
88
Preliminary
CS4041