F84045 Asiliant Technologies, F84045 Datasheet - Page 138

• Manufacturer Part Number: F84045
• Manufacturer: Asiliant Technologies

Specifications of F84045

• Lead Free Status / Rohs Status: Not Compliant

Controller Input Buffer. The controller has a single 8-bit Input Buffer that receives all writes to either 60h or 64h.
Status bit 1 indicates whether or not the previous write is still being processed, and bit 3 indicates whether the write
was a host command (64h) or data (60h).
Controller Output Buffer. The controller also has a single 8-bit Output Buffer that holds all data for reading by the
host CPU at address 60h. Status bit 0 indicates whether or not there is data available to read. If the host CPU isn't
expecting a response to a previous host command, the data read from 60h will be either keyboard data or mouse data,
as indicated by status bit 5. Reading from 60h also clears any pending mouse or keyboard interrupt. Address 60h
should not be read unless status bit 0 is '1'.
Writing to 60h. I/O address 60h should not be written unless status bit 1 is '0'. If the Controller isn't expecting data
associated with a previous host command, data written to I/O address 60h is transmitted to the keyboard as a keyboard
command. (Commands can be transmitted to the mouse via host command code D4h, described below.)
Writing to 64h. Host commands should not be written unless status bit 1 is '0'. In addition, host commands that
generate a read data response should not be issued until the keyboard and mouse have been disabled and any data
already in the Controller Output Buffer has been read. Otherwise, data from the keyboard or mouse could be
overwritten by the command response.
Interrupts. IRQ1 can be enabled as the keyboard interrupt, and IRQ12 can be enabled as the mouse interrupt. Both
interrupts are latched in the 4045 until cleared by a read from I/O address 60h. Interrupt information is communicated
from the 4041 to the 4045 via the Control Link.
System Flag. Status bit 2 has no direct effect on the controller. It is written by the host CPU (via the 60h command
described below), usually to indicate the reason for a CPU reset. On 80286-based systems, CPU reset was the only way
to return from Protected Mode to Real Mode. 386 and 486 systems remain compatible with this method.
Keyboard Inhibit Input. The LDEV2# pin optionally can be programmed to function as a standard Keyboard Inhibit
input (KBINH#) via Index 3Ch, bits 3:2. When the pin is so enabled and driven low, the internal keyboard controller
discards any scan codes received from the keyboard. The keyboard is not prevented from continuing to send scan
codes, and the host CPU can still send commands to the keyboard, but scan codes received from the keyboard are not
given to the host CPU. The keyboard inhibit signal can be overridden by host CPU command 60h (see next section).
The state of the KBINH# signal can be read at any time via port 64h. Mouse operation is not affected by KBINH#.
5.15.1. Host CPU Commands
The 4041 internal keyboard/mouse controller supports the host CPU commands listed below. Unless otherwise noted,
all commands execute in the same ISA cycle in which they are issued.
Revision 1.0
20h
21-2Fh
60h
61-6Fh
A7h
A8h
A9h
AAh
ABh
ADh
AEh
Read Command Byte
Read RAM (one-byte simulated RAM)
Write Command Byte
Write RAM (one-byte simulated RAM)
Disable Mouse
Enable Mouse
Mouse Interface Test
Self Test
Keyboard Interface Test
Disable Keyboard
Enable Keyboard
2/10/95
Subject to change without notice
137
Preliminary
Functional Description
CS4041